AZ10LVE111E driver equivalent, ecl/pecl 1:9 differential clock driver.
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* Operating Range of 3.0V to 5.5V Low Skew Guaranteed Skew Spec Differential Design Enable VBB Output 75kΩ Internal Input Pu.
the VBB reference should be connected to one side of the IN/IN ¯¯ differential input pair. The input signal is then fed.
The AZ10/100LVE111E is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The IN signal is fanned-out to nine identical differential outputs. An Enable input is also provided. A HIGH disables the device by forcing all Q .
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