AZ10LVEL16 Datasheet | Arizona Microtek

FEATURES - - - - - 250ps Propagation Delay High Bandwidth Output Transitions Operating Range of 3.0V to 5.5V Internal Input Pulldown Resistors Direct Replacement For ON Semiconductor MC10EL16, MC100EL16, & MC100LVEL16 PACKAGE SOIC 8 SOIC 8 TSSOP 8 TSSOP 8 Ro HS pliant / Lead (Pb) Free TSSOP 8 TSSOP 8 Ro HS pliant / Lead (Pb) Free 1 2 ARIZONA MICROTEK, INC. ECL/PECL Differential Receiver PACKAGE AVAILABILITY PART NUMBER AZ10LVEL16D AZ100LVEL16D AZ10LVEL16T AZ10LVEL16T+ AZ100LVEL16T AZ100LVEL16T+ MARKING AZM10 LVEL16 AZM100 LVEL16 AZT LV16 AZT+ LV16 AZH LV16 AZH+ LV16 NOTES 1,2 1,2 1,2 1,2 1,2 1,2 DESCRIPTION Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts) Tape & Reel. Date code format: “Y” or “YY” for year followed by “WW” for week on underside of part. The AZ10/100LVEL16 is a differential receiver. The device is functionally equivalent to the E116 device with higher performance capabilities. With output transition times significantly faster than the E116, the LVEL16 is ideally suited for interfacing with high frequency sources. The LVEL16 provides a VBB output for single-ended use or a DC bias reference for AC coupling to the ¯ device. For single-ended input applications, the VBB reference should be connected to one side of the D/D differential input pair. The input signal is then fed to the other D/D ¯ input. The VBB pin can support 1.5 m A sink/source current. When used, the VBB pin should be bypassed to ground via a 0.01 µF capacitor. Under open input conditions internal input clamps will force the Q output LOW. NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established. LOGIC DIAGRAM AND PINOUT ASSIGNMENT PIN DESCRIPTION PIN D, D ¯ Q, Q ¯ VBB VCC VEE NC FUNCTION Data Inputs Data Outputs Reference Voltage Output Positive Supply Negative Supply No Connect 1630 S. STAPLEY DR., SUITE 125 - MESA, ARIZONA 85204 - USA - (480) 962-5881 - FAX...