AT49LD3200B Overview
Synchronous design allows precise cycle control. I/O transactions are possible on every clock cycle. All operations are synchronized to the rising edge of the system clock.
AT49LD3200B Key Features
- 3.0V to 3.6V Read/Write
- Burst Read Performance
- <100 MHz (RAS Latency = 2, CAS Latency = 6), 10 ns Cycle Time tSAC = 7 ns
- <75 MHz (RAS Latency = 2, CAS Latency = 5), 13 ns Cycle Time tSAC = 8 ns
- <50 MHz (RAS Latency = 1, CAS Latency = 4), 20 ns Cycle Time tSAC = 9 ns MRS Cycle with Address Key Programs
- RAS Latency (1 and 2)
- CAS Latency (2 ~ 8)
- Burst Length: 4, 8
- Burst Type: Sequential and Interleaved Word Selectable Organization
- 16 (Word Mode)/x 32 (Double Word Mode) Sector Erase Architecture