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Brilliance Semiconductor

BS616LV2016 Datasheet Preview

BS616LV2016 Datasheet

Very Low Power CMOS SRAM

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Very Low Power CMOS SRAM
128K X 16 bit
Pb-Free and Green package materials are compliant to RoHS
BS616LV2016
n FEATURES
Ÿ Wide VCC operation voltage : 2.4V ~ 5.5V
Ÿ Very low power consumption :
VCC = 3.0V Operation current : 30mA (Max.) at 55ns
2mA (Max.) at 1MHz
Standby current : 0.1uA (Typ.) at 25 OC
VCC = 5.0V Operation current : 62mA (Max.) at 55ns
8mA (Max.) at 1MHz
Standby current : 0.6uA (Typ.) at 25OC
Ÿ High speed access time :
-55 55ns(Max.) at VCC=3.0~5.5V
-70 70ns(Max.) at VCC=2.7~5.5V
Ÿ Automatic power down when chip is deselected
Ÿ Easy expansion with CE and OE options
Ÿ I/O Configuration x8/x16 selectable by LB and UB pin.
Ÿ Three state outputs and TTL compatible
Ÿ Fully static operation
Ÿ Data retention supply voltage as low as 1.5V
n POWER CONSUMPTION
n DESCRIPTION
The BS616LV2016 is a high performance, very low power CMOS
Static Random Access Memory organized as 131,072 by 16 bits and
operates form a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical CMOS standby
current of 0.1uA at 3.0V/25OC and maximum access time of 55ns at
3.0V/85OC.
Easy memory expansion is provided by an active LOW chip enable
(CE) and active LOW output enable (OE) and three-state output
drivers.
The BS616LV2016 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BS616LV2016 is available in DICE form, JEDEC standard
44-pin TSOP II package and 48-ball BGA package.
PRODUCT
FAMILY
OPERATING
TEMPERATURE
STANDBY
(ICCSB1, Max)
VCC=5.0V VCC=3.0V
BS616LV2016DC
BS616LV2016EC
Commercial
+0OC to +70OC
6.0uA
0.7uA
POWER DISSIPATION
1MHz
VCC=5.0V
10MHz
Operating
(ICC, Max)
fMax.
1MHz
VCC=3.0V
10MHz
7mA 39mA 60mA 1.5mA 14mA
PKG TYPE
fMax.
29mA
DICE
TSOP II-44
BS616LV2016AI
BS616LV2016EI
Industrial
-40OC to +85OC
20uA
2.0uA
8mA
40mA 62mA
2mA
15mA
30mA
BGA-48-0608
TSOP II-44
n PIN CONFIGURATIONS
A4 1
44 A5
A3 2
43 A6
A2 3
42 A7
A1 4
41 OE
A0 5
40 UB
CE 6
39 LB
DQ0 7
38 DQ15
DQ1 8
37 DQ14
DQ2 9
36 DQ13
DQ3
VCC
10
11
BS616LV2016EC
35
34
DQ12
VSS
VSS 12 BS616LV2016EI
DQ4 13
33 VCC
32 DQ11
DQ5 14
31 DQ10
DQ6 15
30 DQ9
DQ7 16
29 DQ8
WE 17
28 NC
A16 18
27 A8
A15 19
26 A9
A14 20
25 A10
A13 21
24 A11
A12 22
23 NC
123456
A LB OE A0 A1 A2 NC
B D8 UB A3 A4 CE D0
C D9 D10 A5 A6 D1 D2
D VSS D11 NC A7 D3 VCC
E VCC D12 NC A16 D4 VSS
F D14 D13 A14 A15 D5 D6
G D15 NC A12 A13 WE D7
H NC A8 A9 A10 A11 NC
n BLOCK DIAGRAM
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
DQ0
.
.
.
.
.
.
DQ15
CE
WE
OE
UB
LB
VCC
VSS
Address
Input
Buffer
10
Row
Decoder
1024
Memory Array
1024 x 2048
16
.
.
.
. 16
.
.
Control
Data
Input
Buffer
16
Data
Output
Buffer
16
2048
Column I/O
Write Driver
Sense Amp
128
Column Decoder
7
Address Input Buffer
A12 A13 A14 A15 A16 A0 A1
48-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.
R0201-BS66LV2016
1
Revision 1.4
Nov.
2006




Brilliance Semiconductor

BS616LV2016 Datasheet Preview

BS616LV2016 Datasheet

Very Low Power CMOS SRAM

No Preview Available !

n PIN DESCRIPTIONS
BS616LV2016
Name
A0-A16 Address Input
Function
These 17 address inputs select one of the 131,072 x 16-bit in the RAM
CE Chip Enable Input
WE Write Enable Input
OE Output Enable Input
LB and UB Data Byte Control Input
CE is active LOW. Chip enable must be active when data read form or write to the
device. If chip enable is not active, the device is deselected and is in standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
Lower byte and upper byte data input/output control pins.
DQ0-DQ15 Data Input/Output
Ports
VCC
VSS
There 16 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
n TRUTH TABLE
MODE
CE WE OE LB UB
Chip De-selected
H
X
X
X
X
(Power Down)
X
X
X
H
H
LHH L X
Output Disabled
L HH X L
LL
Read
LHLHL
LH
LL
Write
L LXHL
LH
NOTES: H means VIH; L means VIL; X means dont care (Must be VIH or VIL state)
IO0~IO7
High Z
High Z
High Z
High Z
DOUT
High Z
DOUT
DIN
X
DIN
IO8~IO15
High Z
High Z
High Z
High Z
DOUT
DOUT
High Z
DIN
DIN
X
VCC CURRENT
ICCSB, ICCSB1
ICCSB, ICCSB1
ICC
ICC
ICC
ICC
ICC
ICC
ICC
ICC
R0201-BS616LV2016
2
Revision 1.4
Nov.
2006


Part Number BS616LV2016
Description Very Low Power CMOS SRAM
Maker Brilliance Semiconductor
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BS616LV2016 Datasheet PDF






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