BCM87326 phy equivalent, 7-nm 16 x 56-gb/s pam-4 duplex phy.
* Host-side interface:
– Long reach (LR): ~30 dB
* Line-side interface:
– KR
– CR
– Chip-to-module.
On-chip clock synthesis is performed by a low-cost reference clock through high-frequency, low-jitter phaselocked loops.
5
1.1 Device Functions 6 1.2 High-Speed Transmitter .........6 1.3 High-Speed Receiver ....6
1.3.1 Peaking Filter and VGA ..6 1.3.2 Decision Feedback Equalizer (DFE)/Timing Recovery .....6 1.4 Adaptive Voltage Scaling .......7 1.5 Loss-of-Signal and.
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