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CX50561 Datasheet Preview

CX50561 Datasheet

(CX5000 Series) Structured ASIC

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CX50561 pdf
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DATASHEET
CX5000
0.18um Structured ASIC
Product Description
The 0.18um CX5000 is an ASIC that utilizes the combination of an
advanced metal programmable gate array and optimized EDA system to
implement high performance ASIC designs while reducing application
tooling costs and design turnaround time. ASIC designers using the
CX5000 are able to meet or exceed their design schedules and budgets
without compromising technical objectives.
The CX5000 comprises a family of pre-configured platform masterslices that
contain varying amounts of general-purpose logic, fast memory, advanced
I/Os, clock synthesis and phase management macrocells. When combined with a mix of popular third-
party tools and custom designed point EDA solutions, the CX5000 provides not just gate array hardware,
but also a complete ASIC Platform from which to develop today’s advanced SoC ASICs.
Manufactured in UMC’s 0.18um, 6-layer metal CMOS process, the CX5000 combines the reliability and
quality of an industry-leading silicon foundry, with the high performance, low power consumption and fast
design turnaround time of ChipX Structured ASIC technology. The CX5000 family is very applicable to
cost reduction projects, replacing expensive FPGA devices with low-cost metal programmable
technology. The CX5000 is the first viable “standard cell alternative” ASIC technology, developed in
response to the growing need for cost-effective ASIC implementation capability.
The CX5000 Structured ASIC technology uses just two of the six available metal layers to program the
logic, memory, I/O and clocking of an ASIC design and so eliminates the large costs of the remaining
“fixed” masks. Wafers are manufactured up to Metal 4, where they are held pending completion of the
customer application. Completed chips can be delivered to the customer less than three weeks after sign-
off of the finished design.
ChipX Structured ASIC technology is very similar in concept to FPGA, which makes it easy to use and
familiar to most ASIC and system designers. Using metal interconnect segments rather than SRAM cells
to program the ASIC, CX5000 technology reduces the area of the chip by between 5x and 10x over the
equivalent FPGA and brings performance up to 90% of standard cell design speeds.
Key Features and Benefits
mStructured ASIC architecture
.coLow NRE and start-up costs
UFast time to production
t430K to 1.2M usable ASIC gates
eUp to 2.6M bits of fast block memory
he2ns access time single-port SRAM, dual-port SRAM and ROM
SLow power consumption (0.06uW/MHz/Gate)
ta200MHz general core logic operation, 650MHz in constrained clock domains
www.Da© ChipX Inc.
1
CEC034 (9/20/05)



Chip Express
Chip Express

CX50561 Datasheet Preview

CX50561 Datasheet

(CX5000 Series) Structured ASIC

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CX50561 pdf
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CX5000:
0.18um Structured ASIC Product Family
PCI, PCI-X, SSTL, HSTL, USB1.1, RSDS, LVPECL and LVDS up to 622Mbps
1.5V or 1.8V or mixed supply voltage operation
Up to 1100 total pads
Low-jitter analog PLL macros with internal loop filter
Delay Lock Loop (DLL) macros for clock de-skewing
Wide range of synthesizable IP cores such as CPUs and interface controllers
Vast packaging library
Standard ASIC tool flow
Available front-end and FPGA conversion design services
BIST and Scan synthesis test options
Seamless migration to Standard Cell in high volume
Excellent for SoC designs, new ASICs, and FPGA conversion
The CX5000 Structured ASIC “System Slice”
The CX5000 System Slice product line is designed to incorporate a mix of gates and memory optimized
for a wide range of today’s advanced SoCs. With a ratio of approximately 160% memory to gates, each
slice contains enough memory to support CPU cache, network rate-matching FIFOs, multiple video line
buffers and various other single- or dual-port applications.
The CX5000 System-Slice arrays shown in Table 1 have a variety of gate and memory counts. The
maximum usable gates in each array is design dependent and refers to the actual size of a customer
design prior to test insertion or timing closure.
BASE
ARRAY
CX50041
CX50101
CX50211
CX50331
CX50561
CX50841
CX51191
CX51761
TABLE 1.
CX5000 SYSTEM SLICE
MAX USABLE
FAST BLOCK
ASIC GATES (K)
SRAM (K)
30-40
64
91-101
160
131-144
364
207-228
518
336-369
880
526-578
1264
716-787
1774
1108-1219
2582
LOW JITTER
APLL/DLL
4/2
4/8
4/8
4/8
4/12
4/12
4/12
4/12
BOND
PADS
128
256
384
448
640
768
896
1152
There are a fixed number of block memories on each masterslice for speed, and for logic and memory
efficiency. Each slice has a total available memory count, which can be split into either 18K, 16K or 8K
blocks in a variety of widths and depths, or double-pumped to create smaller memories. The memory can
mbe configured as single- or dual-port RAM/ROM, as required.
.coChipX uses the latest clock synthesis techniques during layout of the Structured ASIC. We provide the
Uuser with four complete analog PLL units for clock phase alignment (when needed), frequency synthesis,
t4or stabilization. These PLL macros have excellent jitter performance and incorporate all of the analog
ecomponents needed for supply and loop filtering on board the masterslice. A DLL macro generator is
heavailable for clock-edge alignment in timing-critical applications.
www.DataS© ChipX Inc.
2 CEC034 (9/20/05)


Part Number CX50561
Description (CX5000 Series) Structured ASIC
Maker Chip Express
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