CG7480AT Datasheet | Cypress

Features - Temperature ranges - - 40 °C to 125 °C - High speed - t AA = 15 ns - Low active power - ICC = 120 m A at 67 MHz - Low CMOS standby power - ISB2 = 20 m A - 2.0-V data retention - Automatic power-down when deselected - Transistor-transistor logic (TTL)-patible inputs and outputs - Easy memory expansion with CE and OE features - Available in Pb-free 44-pin thin small outline package (TSOP) II. Functional Description The CG7480AT is a high performance CMOS Static RAM organized as 512 K words by 16 bits. To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte LOW Enable (BLE) is LOW, then data from I/O pins (I/O0- I/O7), is written into the location specified on the address pins (A0- A18). If Byte HIGH Enable (BHE) is LOW, then data from I/O pins (I/O8- I/O15) is written into the location specified on the address pins (A0- A18). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte LOW Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O0- I/O7. If Byte HIGH Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See the Truth Table on page 11 for a plete description of read and write modes. The input/output pins (I/O0- I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or a write operation (CE LOW, and WE LOW) is in progress. The CG7480AT is available in a 44-pin TSOP II package with center power and ground (revolutionary) pinout. Logic Block Diagram ROW DECODER SENSE AMPS INPUT BUFFER A0 A1 A2 AA34 AA56 512 K × 16 ARRAY AA78 COLUMN DECODER I/O0- I/O7 I/O8- I/O15 A9 AA1101 AA1123 A14 A15 A16 AA1178 WE CE OE BLE Cypress Semiconductor Corporation - 198 Champion Court Document Number: 001-73191 Rev. - A - San Jose, CA 95134-1709 - 408-943-2600 Revised April 4,...