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Cypress Semiconductor Electronic Components Datasheet

CY2308 Datasheet

3.3V Zero Delay Buffer

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CY2308
3.3 V Zero Delay Buffer
3.3 V Zero Delay Buffer
Features
Zero input-output propagation delay, adjustable by capacitive
load on FBK input
Multiple configurations, see Available CY2308 Configurations
on page 4 for more details
Multiple low skew outputs
Two banks of four outputs, three-stateable by two select inputs
10 MHz to 133 MHz operating range
75 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)
Space saving 16-pin 150 mil SOIC package or 16-pin TSSOP
3.3 V operation
Industrial temperature available
Functional Description
The CY2308 is a 3.3 V Zero Delay Buffer designed to distribute
high speed clocks in PC, workstation, datacom, telecom, and
other high performance applications.
The part has an on-chip PLL that locks to an input clock
presented on the REF pin. The PLL feedback is driven from
external FBK pin, so user has flexibility to choose any one of the
outputs as feedback input and connect it to FBK pin. The
input-to-output skew is less than 250 ps and output-to-output
skew is less than 200 ps.
The CY2308 has two banks of four outputs each that is controlled
by the select inputs as shown in the table Select Input Decoding
on page 3. If all output clocks are not required, Bank B is
three-stated. The input clock is directly applied to the output for
chip and system testing purposes by the select inputs.
The CY2308 PLL enters a power down state when there are no
rising edges on the REF input. In this mode, all outputs are
three-stated and the PLL is turned off resulting in less than 25 A
of current draw. The PLL shuts down in two additional cases as
shown in the table Select Input Decoding on page 3.
Multiple CY2308 devices accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is less than 700 ps.
The CY2308 is available in five different configurations as shown
in the table Available CY2308 Configurations on page 4.
The CY2308-1 is the base part where the output frequencies
equal the reference if there is no counter in the feedback path.
The CY2308-1H is the high drive version of the -1 and rise and
fall times on this device are much faster.
The CY2308-2 enables the user to obtain 2x and 1x frequencies
on each output bank. The exact configuration and output
frequencies depend on the user’s selection of output that drives
the feedback pin.
The CY2308-3 enables the user to obtain 4x and 2x frequencies
on the outputs.
The CY2308-4 enables the user to obtain 2x clocks on all
outputs. Thus, the part is extremely versatile and is used in a
variety of applications.
The CY2308-5H is a high drive version with REF/2 on both
banks.
For a complete list of related documentation, click here.
Logic Block Diagram
/2
REF
/2
PLL
Extra Divider (–3, –4)
Extra Divider (–5H)
S2 Select Input
S1 Decoding
MUX
/2
Extra Divider (–2, –3)
FBK
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-07146 Rev. *T
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 7, 2017


Cypress Semiconductor Electronic Components Datasheet

CY2308 Datasheet

3.3V Zero Delay Buffer

No Preview Available !

CY2308
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Select Input Decoding ...................................................... 3
Available CY2308 Configurations ................................... 4
Zero Delay and Skew Control .......................................... 4
Maximum Ratings ............................................................. 5
Operating Conditions ....................................................... 5
Electrical Characteristics ................................................. 5
Operating Conditions ....................................................... 6
Electrical Characteristics ................................................. 6
Thermal Resistance .......................................................... 6
Switching Characteristics ................................................ 7
Switching Characteristics ................................................ 8
Switching Waveforms ...................................................... 9
Typical Duty Cycle and IDD Trends .............................. 10
Typical Duty Cycle and IDD Trends .............................. 11
Test Circuits .................................................................... 12
Ordering Information ...................................................... 13
Ordering Code Definitions ......................................... 14
Package Diagrams .......................................................... 15
Acronyms ........................................................................ 16
Document Conventions ................................................. 16
Units of Measure ....................................................... 16
Errata ............................................................................... 17
Part Numbers Affected .............................................. 17
CY2308 Errata Summary .......................................... 17
CY2308 Qualification Status ..................................... 17
Document History Page ................................................. 19
Sales, Solutions, and Legal Information ...................... 21
Worldwide Sales and Design Support ....................... 21
Products .................................................................... 21
PSoC®Solutions ....................................................... 21
Cypress Developer Community ................................. 21
Technical Support ............................................................. 21
Document Number: 38-07146 Rev. *T
Page 2 of 21


Part Number CY2308
Description 3.3V Zero Delay Buffer
Maker Cypress
Total Page 21 Pages
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