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CY7C342B - 128-Macrocell MAX EPLDs

General Description

The CY7C342B is an Erasable Programmable Logic Device (EPLD) in which CMOS EPROM cells are used to configure logic functions within the device.

The MAX architecture is 100% user configurable, allowing the devices to accommodate a variety of independent logic functions.

Key Features

  • 128 macrocells in 8 LABs.
  • 8 dedicated inputs, 52 bidirectional I/O pins.
  • Programmable interconnect array.
  • Advanced 0.65-micron CMOS technology to increase performance.
  • Available in 68-pin HLCC, PLCC, and PGA Functional.

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Full PDF Text Transcription for CY7C342B (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for CY7C342B. For precise diagrams, and layout, please refer to the original PDF.

fax id: 61071CY7C342B CY7C342B Features • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • Advanced 0.65-micro...

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ional I/O pins • Programmable interconnect array • Advanced 0.65-micron CMOS technology to increase performance • Available in 68-pin HLCC, PLCC, and PGA Functional Description The CY7C342B is an Erasable Programmable Logic Device (EPLD) in which CMOS EPROM cells are used to configure logic functions within the device. The MAX architecture is 100% user configurable, allowing the devices to accommodate a variety of independent logic functions. Logic Block Diagram 1 (B6) INPUT/CLK 2 (A6) INPUT 32 (L4) INPUT 34 (L5) INPUT 128-Macrocell MAX® EPLDs The 128 macrocells in the CY7C342B are divided into 8 Logic Array Blocks (LABs),

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