CYDC128B16 Datasheet | Cypress

Features - True dual-ported memory cells which allow simultaneous access of the same memory location - 4/8/16K × 16 and 8/16K × 8 organization - High speed access: 40 ns - Ultra low operating power - Active: ICC = 15 m A (typical) at 55 ns - Active: ICC = 25 m A (typical) at 40 ns - Standby: ISB3 = 2 μA (typical) - Port-independent 1.8 V, 2.5 V, and 3.0 V I/Os - Pb-free 14 × 14 × 1.4 mm 100-pin Thin Quad Flat Pack (TQFP) Package - Full asynchronous operation - Pin select for master or slave - Expandable data bus to 32 bits with master/slave chip select when using more than one device - On-chip arbitration logic - On-chip semaphore logic - Input read registers (IRR) and output drive registers (ODR) - INT flag for port-to-port munication - Separate upper byte and lower byte control - mercial and industrial temperature ranges Functional Description The CYDC128B16 is a low power plementary metal oxide semiconductor (CMOS) 4K, 8K,16K × 16, and 8/16K × 8 dual-port static RAM. Arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be used as standalone 16-bit dual-port static RAMs or multiple devices can be bined in order to function as a 32-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 32-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, munications status buffering, and dual-port video/graphics memory. Each port has independent control pins: Chip Enable (CE), Read or Write Enable (R/W), and Output Enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag (INT) permits...