MB90V495G Datasheet | Cypress

Features Clock - Built-in PLL clock frequency multiplication circuit - Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and multiplication of 1 to 4 times of oscillation clock (for 4-MHz oscillation clock, 4 MHz to 16 MHz). - Operation by sub-clock (8.192 k Hz) is allowed. (MB90387, MB90F387) - Minimum execution time of instruction: 62.5 ns (when operating with 4-MHz oscillation clock, and 4-time multiplied PLL clock). 16 Mbyte CPU memory Space - 24-bit internal addressing Instruction System Best Suited to Controller - Wide choice of data types (bit, byte, word, and long word) - Wide choice of addressing modes (23 types) - Enhanced multiply-divide instructions and RETI instructions - Enhanced high-precision puting with 32-bit accumulator Instruction System patible with High-level Language (C language) and Multitask - Employing system stack pointer - Enhanced various pointer indirect instructions - Barrel shift instructions Increased Processing Speed - 4-byte instruction queue Powerful Interrupt Function with 8 Levels and 34 Factors Automatic Data Transfer Function Independent of CPU - Expanded intelligent I/O service function (EI2 OS): Maximum of 16 channels Low Power Consumption (standby) Mode - Sleep mode (a mode that halts CPU operating clock) - Time-base timer mode (a mode that operates oscillation clock, sub clock, time-base timer and watch timer only) - Watch mode (a mode that operates sub clock and watch timer only) - Stop mode (a mode that stops oscillation clock and sub clock) - CPU blocking operation mode Process - CMOS...