MB90V495G Overview
The devices of this series have the built-in full-CAN interface. The system, inheriting the architecture of F2MC family, employs additional instruction ready for high-level languages, expanded addressing mode, enhanced multiply-divide instructions, and enriched bit-processing instructions. Furthermore, employment of 32bit accumulator achieves processing of long-word data (32 bits).
MB90V495G Key Features
- Built-in PLL clock frequency multiplication circuit
- Selection of machine clocks (PLL clocks) is allowed among
- Operation by sub-clock (8.192 kHz) is allowed. (MB90387, MB90F387)
- Minimum execution time of instruction: 62.5 ns (when operating with 4-MHz oscillation clock, and 4-time multiplied PLL c
- 24-bit internal addressing
- Wide choice of data types (bit, byte, word, and long word)
- Wide choice of addressing modes (23 types)
- Enhanced multiply-divide instructions and RETI instructions
- Enhanced high-precision puting with 32-bit accumulator
- Employing system stack pointer
