Description
4
HyperBus Interface 4 Product Overview 6
HyperBus Interface 6 Signal Description 7
Input/Output Summary 7 HyperBus Transaction Details 8
Command/Address Bit Assignments 8 Read Transactions 12 Write Transactions (Memory Array Write) 13 Write Transactions without Initial Latency (Register Write) 15 Memory Space 16 HyperBus Interface 16 Register Space 16 HyperBus Interface 16 Device Identification Registers 17 Register Space Access 18 Interface States 23 Power Conservation Modes
Features
- Interface.
- HyperBus Interface.
- 1.8 V / 3.0 V interface support.
- Single-ended clock (CK) - 11 bus signals.
- Optional differential clock (CK, CK#) - 12 bus signals.
- Chip Select (CS#).
- 8-bit data bus (DQ[7:0]).
- Hardware reset (RESET#).
- Bidirectional Read-Write Data Strobe (RWDS).
- Output at the start of all transactions to indicate refresh latency.
- Output during read transactions as Read Data Strobe.
- Input during write transactions as Write Data.
S27KL0642-Cypress.pdf
