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CB664
I2C Clock Distribution Buffer for Three Banks of Mobile SDRAM
Approved Product
Product Features
• 7 output buffer for high clock fanout applications.
• Output may be individually disabled with I2C
• VDD = 3.3 volts
• Output frequency range 10 MHz to 100 MHz
• <250ps skew between output clocks.
• 16-pin SSOP and TSSOP package.
Block Diagram
SDATA
SCLK
REFIN
I2C Control
VDD
2
1
2
2
SDR(0:1)
SDR2
SDR(3:4)
SDR(5:6)
Product Description
The device is a high fanout system clock buffer. Its
primary application is to distribute clocks needed to
support a wide range of applications such as SDRAM
clocks. This device provides low skew distribution
clock heavily loaded. One important application of
this component is where long traces are used to
transport clocks from their generating devices to their
loads. The creation of EMI and the degradation of
waveform rise and fall times is greatly reduces by
running a single reference clock trace to this device
and then using it to these devices EMI is therefore
minimized and board real estate is saved.
Pin Configuration
VDD
SDR0
SDR1
VSS
CLKIN
SDR2
VDD
SDATA
1
2
3
4
5
6
7
8
16 SDR6
15 SDR5
14 VSS
13 VDD
12 SDR4
11 SDR3
10 VSS
9 SCLK
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07024 Rev. **
5/6/99
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