CY14V104NA Datasheet | Cypress

CY14V104LA CY14V104NA 4-Mbit (512 K × 8 / 256 K × 16) nv SRAM 4-Mbit (512 K × 8 / 256 K × 16) nv SRAM Features - - - - - - - - - - - - Functional Description The Cypress CY14V104LA/CY14V104NA is a fast static RAM, with a non-volatile element in each memory cell. The memory is organized as 512 K bytes of 8 bits each or 256 K words of 16 bits each. The embedded non-volatile elements incorporate Quantum Trap technology, producing the world’s most reliable non-volatile memory. The SRAM provides infinite read and write cycles, while independent non-volatile data resides in the highly reliable Quantum Trap cell. Data transfers from the SRAM to the non-volatile elements (the STORE operation) takes place automatically at power-down. On power-up, data is restored to the SRAM (the RECALL operation) from the non-volatile memory. Both the STORE and RECALL operations are also available under software control. 25 ns and 45 ns access times Internally organized as 512 K × 8 (CY14V104LA) or 256 K × 16 (CY14V104NA) Hands off automatic STORE on power-down with only a small capacitor STORE to Quantum Trap non-volatile elements initiated by software, device pin, or Auto Store on power-down RECALL to SRAM initiated by software or power-up Infinite read, write, and recall cycles 1-million STORE cycles to Quantum Trap 20 year data retention Core VCC = 3.0 V to 3.6 V; IO VCCQ = 1.65 V to 1.95 V Industrial temperature 48-ball fine-pitch ball grid array (FBGA) package Pb-free and restriction of hazardous substances (Ro HS) pliance Logic Block Diagram [1, 2, 3] Quatrum Trap 2048 X 2048 A0 A1 A2 A3 A4 A5 A6 A7 A8 A17 A18 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 A9 A10 A11 A12 A13 A14 A15 A16 CE BLE I N P U T B U F F E R S R O W D E C O D E R STORE RECALL STATIC RAM ARRAY 2048 X 2048 STORE/RECALL CONTROL HSB VCC VCCQ VCAP POWER CONTROL SOFTWARE DETECT A14 - A2 COLUMN I/O COLUMN DEC OE WE Notes 1. Address A0- A18 for × 8 configuration and Address A0- A17...