Datasheet Summary
CY2305C CY2309C
3.3 V Zero Delay Clock Buffer
3.3 V Zero Delay Clock Buffer
Features
- 10 MHz to 100- 133 MHz operating range
- Zero input and output propagation delay
- Multiple low skew outputs
- One input drives five outputs (CY2305C)
- One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309C)
- 50 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)
- Test mode to bypass phase locked loop (PLL) (CY2309C) only, see Select Input Decoding on page 6
- Available in space saving 16-pin 150 Mil small outline integrated circuit (SOIC) or 4.4 mm thin shrunk small outline package (TSSOP) packages (CY2309C), and 8-pin, 150 Mil SOIC package (CY2305C)
- 3.3 V operation
- mercial, industrial and...
