May 10, 2007
Errata Document for CY2305C, CY2309C Zero Delay Buffers
Errata Revision: [**]
This document describes the errata for the Zero Delay Clock Buffers, CY2305C and CY2309C. Details include errata
trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Compare this document
to the device’s data sheet for a complete functional description.
Contact your local Cypress Sales Representative if you have questions.
Part Numbers Affected
Zero Delay Buffer Qualification Status
Zero Delay Buffer Errata Summary
The following table defines the errata applicability to available Zero Delay Buffer family devices.
Note Errata titles are hyperlinked. Click on the table item entry to jump to its description.
 Possible increased power down current
Will be corrected in the next silicon revision. The
errata is forecast to be corrected for all devices
dated October 2007 and later.
1. Possible increased power down current
• PROBLEM DEFINITION
When the device is in the power down state, an unbonded pad on the die is allowed to float. Because of this,
power down current may exceed the data sheet limit.
While high current draw is theoretically possible any time during power down, it has only been observed as a
transient occurrence shortly after the device enters power down. Steady-state current has always been ob-
served to be within data sheet limits.
• PARAMETERS AFFECTED
IDD (PD Mode)
Data Sheet Maximum
• TRIGGER CONDITION(S)
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134 • 408.943.2600
Document Number: 001-15585 Rev. **
Revised May 10, 2007