CY26049-36 Description
8 kHz or high impedance in buffer mode. Determines CLK outputs per Table 1. Determines CLK outputs per Table.
CY26049-36 Key Features
- Fully integrated phase-locked loop (PLL)
- FailSafe output
- PLL driven by a crystal oscillator that is phase aligned with external reference
- Output frequencies selectable and/or programmed to standard munication frequencies
- Low-jitter, high-accuracy outputs
- mercial and Industrial operation
- 3.3V ± 5% operation
- 16-lead TSSOP
- When reference is in range, SAFE pin is driven high
- When reference is off, DCXO maintains clock outputs. SAFE pin is low