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Cypress Semiconductor Electronic Components Datasheet

CY26126 Datasheet

Dual Output 125-MHz Clock Generator

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5
Advance Information
CY26126
Dual Output 125-MHz
Clock Generator
Features
• Integrated phase-locked loop
• Low skew, low jitter, high accuracy outputs
• 3.3V Operation
Part Number Outputs
CY26126
2
Input Frequency Range
25 MHz
Logic Block Diagram
Benefits
Highest-performance PLL tailored for multimedia applications
Meets critical timing requirements in complex system designs
Output Frequencies
2 copies of 125 MHz (3.3V)
25 XIN
XOUT
OSC.
OE
P Comp
Q
VCO
P
PLL
OUTPUT
MULTIPLEXER
AND
DIVIDERS
VDD
VSS
125 MHz
125 MHz
Pin Configurations
CY26126
8-pin SOIC
XIN
VDD
OE
VSS
1
2
3
4
www.DataSheet4U.com
8 XOUT
7 CLKB
6 CLKA
5 VSS
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07351 Rev. *A
Revised December 14, 2002


Cypress Semiconductor Electronic Components Datasheet

CY26126 Datasheet

Dual Output 125-MHz Clock Generator

No Preview Available !

Advance Information
CY26126
Pin Summary
Name
XIN
VDD
OE
VSS
VSS
CLKA
CLKB
XOUT[1]
Pin Number
1
2
3
4
5
6
7
8
Description
Reference Input
3.3V Voltage Supply
Output Enable
Ground
Ground
125-MHz Clock Output A
125-MHz Clock Output B
Reference Output
Absolute Maximum Conditions
Parameter
VDD
TS
TJ
Description
Supply Voltage
Storage Temperature[2]
Junction Temperature
Digital Inputs
Digital Outputs referred to VDD
Electro-Static Discharge
Min.
0.5
65
VSS 0.3
VSS 0.3
2
Recommended Operating Conditions
Parameter
VDD
TA
CLOAD
Pmax
fREF
tPU
Description
Operating Voltage
Ambient Temperature
Max. Load Capacitance
Max. Output Power Dissipation
Reference Frequency
Power-up time for all VDD's to
reach minimum specified voltage
(power ramps must be monotonic)
Min.
3.14
0
0.05
DC Electrical Characteristics
Parameter
Description
Conditions
IOH Output High Current VOH = VDD 0.5, VDD = 3.3V
IOL Output Low Current VOL = 0.5, VDD = 3.3V
VIH Input High Voltage
www.DataShVeILet4U.comInput Low Voltage
CMOS Levels 70% of VDD
CMOS Levels 30% of VDD
CIN Input Capacitance
IIZ Input Leakage Current
IDD Supply Current
Sum of Core and Output Current
Notes:
1. Float XOUT pin if XIN is driven by reference clock (as opposed to crystal).
2. Rated for 10 years.
Document #: 38-07351 Rev. *A
Max.
7.0
125
125
VDD + 0.3
VDD + 0.3
Unit.
V
°C
°C
V
V
kV
Typ.
3.3
25
Max.
3.47
70
15
150
500
Unit
V
°C
pF
mW
MHz
ms
Min.
12
12
0.7
Typ.
24
24
5
Max.
0.3
7
35
Unit
mA
mA
VDD
VDD
pF
µA
mA
Page 2 of 5


Part Number CY26126
Description Dual Output 125-MHz Clock Generator
Maker Cypress Semiconductor
Total Page 5 Pages
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