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Cypress Semiconductor Electronic Components Datasheet

CY28510 Datasheet

Peripheral I/O Clock Generator

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510
CY28510
Features
• 15 33.27-MHz or 66.669-MHz clock outputs
• 1 REF 14.318 MHz
• Divide by 2, spread spectrum and output enable all se-
lectable on a per-output basis via I2C register bits
• Divide by 2 mode default values strappable on a
per-group basis
• Output Enable pin controls all outputs
Block Diagram
Peripheral I/O Clock Generator
• I2C Compatible Programmability With Block and Byte
Modes
• I2C Operates Up to 1MHz
• I2C Address Selection of D0, D2, D4 or D6
• 48 Pin SSOP Package
Pin Configuration
XIN REF
PLL 1with
Spread
Spectrum
66MHz
CLK_STOP#
PLL 2 no
Spread
Spectrum
66MHz
(Group Frequency Select, 33 or 66MHz)
GFS0
SCLK
SDATA
I2C
ADDSEL(0:1)
www.DataSheet4U.com
GFS1
GFS2
GFS3
Mux ÷2
Mux ÷2
Mux ÷2
Mux ÷2
Mux ÷2
Mux ÷2
Mux ÷2
Mux ÷2
Mux ÷2
Mux ÷2
Mux ÷2
Mux ÷2
Mux ÷2
Mux ÷2
Mux ÷2
CLKG0_0
CLKG0_1
CLKG0_2
CLKG0_3
CLKG0_4
CLKG0_5
CLKG0_6
CLKG0_7
CLKG1_0
CLKG1_1
CLKG1_2
CLKG1_3
CLKG2_0
CLKG2_1
CLKG3
GFS3
REF
GFS0
VDDX
VSSX
XIN
XOUT
VDDC
ADDSEL0
ADDSEL1
VSSC
CLK_STOP#
SCLK
SDATA
GFS1
GFS2
OE
CLKG3
VDDQ3
VSSQ3
VSSQ2
CLKG2_1
CLKG2_0
VDDQ2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDQ0
47 CLKG0_0
46 CLKG0_1
45 VSSQ0
44 CLKG0_2
43 VDDQ0
42 VSSQ0
41 CLKG0_3
40 CLKG0_4
39 VDDQ0
38 CLKG0_5
37 CLKG0_6
36 CLKG0_7
35 VSSQ0
34 VDDQ1
33 CLKG1_0
32 CLKG1_1
31 VSSQ1
30 VDDQ1
29 CLKG1_2
28 CLKG1_3
27 VSSQ1
26 VDDA
25 VSSA
OE
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07542 Rev. **
Revised April 28, 2003


Cypress Semiconductor Electronic Components Datasheet

CY28510 Datasheet

Peripheral I/O Clock Generator

No Preview Available !

CY28510
Pin Description
Pin Name
2 REF
6 XIN
Type
O
I
7 XOUT
9 ADDSEL0
10 ADDSEL1
12 CLK_STOP#
13 SCLK
14 SDATA
3 GFS0
15 GFS1
16 GFS2
1 GFS3
17 OE
18 CLKG3
22,23
CLKG2_(1:0)
28,29,32,33 CLKG1_(3:0)
www.Da3ta6S,3he7e,3t48U,4.c0o,m4 CLKG0_(7:0)
1,44,46,47
39 VDDQ0_2
43 VDDQ0_1
48 VDDQ0_0
35 VSSQ0
42 VSSQ0
45 VSSQ0
30 VDDQ1
37 VSSQ1
34 VDDQ1
31 VSSQ1
24 VDDQ2
21 VSSQ2
19 VDDQ3
20 VSSQ3
O
I, PU
250 K
I, PU
250 K
I, PU
250 K
I
I/O
I, PD
250 K
I, PD
250 K
I, PD
250 K
I, PD
250 K
I, PU
250 K
O
O
O
O
PWR
PWR
PWR
GND
GND
GND
PWR
GND
PWR
GND
PWR
GND
PWR
GND
Power
VDDX
VDDX
VDDX
VDDC
VDDC
Description
Reference Clock: 3.3V 14.318-MHz clock output.
Crystal Connection or External Reference Frequency Input: This pin has
dual functions. It can be used as an external 14.318-MHz crystal
connection or as an external reference frequency input.
Crystal Connection for an external 14.318-MHz crystal output.
I2C address selection.
ADDSEL1, ADSEL0: 0,0 = D0; 0,1 = D2, 1,0 = D4, 1,1 = D6
VDDC
VDDC
VDDC
VDDC
Synchronous clock stop pin. When low, all of the clocks except REF are
stopped low after completing a normal positive pulse cycle.
I2C compatible SCLOCK.
I2C compatible SDATA.
Group frequency select 0. 0 = 33 MHz, 1 = 66 MHz.
VDDC Group frequency select 1. 0 = 33 MHz, 1 = 66 MHz.
VDDC Group frequency select 2. 0 = 33 MHz, 1 = 66 MHz.
VDDC Group frequency select 3. 0 = 33 MHz, 1 = 66 MHz.
VDDC Output enable. 1 = enabled, 0 = disabled (tri-state)
VSSQ3
VSSQ2
VSSQ1
VSSQ0
Output clock, group 3, 33 or 66 MHz.
Output clocks, group 2, 33 or 66 MHz.
Output clocks, group 1, 33 or 66 MHz.
Output clocks, group 0, 33 or 66 MHz.
3.3V Power supply for outputs CLKG0_(7:6).
3.3V Power supply for outputs CLKG0_(5:3).
3.3V Power supply for outputs CLKG0_(2:0).
Ground for output buffers CLKG0_(7:6).
Ground for output buffers CLKG0_(5:3).
Ground for output buffers CLKG0_(2:0).
3.3V Power supply for outputs CLKG1_(3:2).
Ground for output buffers CLKG1_(3:2).
3.3V Power supply for outputs CLKG1_(1:0).
Ground for output buffers CLKG1_(1:0).
3.3V Power supply for outputs CLKG2_(1:0).
Ground for output buffers.
3.3V Power supply for outputs.
Ground for output buffers.
Document #: 38-07542 Rev. **
Page 2 of 13


Part Number CY28510
Description Peripheral I/O Clock Generator
Maker Cypress Semiconductor
Total Page 13 Pages
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