CY2PD817 buffer equivalent, pecl/cmos buffer.
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* DC to 320-MHz operation 50-ps output-output skew 30-ps cycle-cycle jitter 2.5V power supply .
requiring mixed differential and single-ended clock distribution. This device accepts an LVPECL input reference clock an.
The CY2PD817 is a low-voltage LVPECL-to-LVPECL and LVCMOS fanout buffer designed for servers, data communications, and clock management. The CY2PD817 is ideal for applications requiring mixed differential and single-ended clock distribution. This dev.
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