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CY7C1012AV33 - 512K x 24 Static RAM

Description

The CY7C1012AV33 is a high-performance CMOS static RAM organized as 512K words by 24 bits.

Each data byte is separately controlled by the individual chip selects (CE0, CE1, CE2).

I/O7, while CE1 controls the data on I/O8 I/O15, and CE2 controls the d

Features

  • High speed.
  • tAA = 8, 10, 12 ns.
  • Low active power.
  • 1080 mW (max. ).
  • Operating voltages of 3.3 ± 0.3V.
  • 2.0V data retention.
  • Automatic power-down when deselected.
  • TTL-compatible inputs and outputs.
  • Easy memory expansion with CE0, CE1 and CE2 features Writing the data bytes into the SRAM is accomplished when the chip select controlling that byte is LOW and the write enable input (WE) input is LOW. Data on the respective.

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CY7C1012AV33 512K x 24 Static RAM Features • High speed — tAA = 8, 10, 12 ns • Low active power — 1080 mW (max.) • Operating voltages of 3.3 ± 0.3V • 2.0V data retention • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE0, CE1 and CE2 features Writing the data bytes into the SRAM is accomplished when the chip select controlling that byte is LOW and the write enable input (WE) input is LOW. Data on the respective input/output (I/O) pins is then written into the location specified on the address pins (A0–A18). Asserting all of the chip selects LOW and write enable LOW will write all 24 bits of data into the SRAM. Output enable (OE) is ignored while in WRITE mode. Data bytes can also be individually read from the device.
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