CY7C1165KV18 architecture equivalent, 18-mbit qdr ii sram four-word burst architecture.
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Configurations
With Read Cycle Latency of 2.5 cycles: CY7C1161KV18
– 2 M x 8 CY7C1176KV18
– 2 M x 9 CY7C1163KV18
– .
The CY7C1161KV18, CY7C1176KV18, CY7C1163KV18, and CY7C1165KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write.
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