Datasheet4U Logo Datasheet4U.com

CY7C1231F - 2Mbit Flow-Through SRAM

Description

The CY7C1231F is a 3.3V, 128K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states.

Features

  • Can support up to 117-MHz bus operations with zero wait states.
  • Data is transferred on every clock w w.
  • Pin compatible and functionally equivalent to ZBT™ devices.
  • Internally self-timed output buffer control to eliminate the need to use OE.
  • Registered inputs for flow-through operation.
  • Byte Write capability.
  • 128K x 18 common I/O architecture.
  • Single 3.3V power supply.
  • Fast clock-to-output times.
  • 7.5 ns.

📥 Download Datasheet

Datasheet preview – CY7C1231F

📁 Similar Datasheet

  • CY7C1006D - 1-Mbit (256K x 4) Static RAM (Cypress)
  • CY7C1011G - 2-Mbit (128K words x 16 bit) Static RAM (Cypress)
  • CY7C1041G - 4-Mbit (256K words x 16 bit) Static RAM (Cypress)
  • CY7C1041GE - 4-Mbit (256K words x 16 bit) Static RAM (Cypress)
  • CY7C1041GN - 4-Mbit (256K words x 16 bit) Static RAM (Cypress)
  • CY7C1049GN - 4-Mbit (512K words x 8 bit) Static RAM (Cypress)
  • CY7C1061DV33 - 16-Mbit (1 M X 16) Static RAM (Cypress)
  • CY7C1061G - 16-Mbit (1 M words x 16 bit) Static RAM (Cypress)
  • CY7C106D - 1-Mbit (256K x 4) Static RAM (Cypress)
  • CY7C131AE - 1K/2K x 8 Dual-Port Static RAM (Cypress)
Other Datasheets by Cypress Semiconductor
  • CY7C1212F - 1-Mbit (64K x 18) Pipelined Sync SRAM
  • CY7C1212H - 1-Mbit (64K x 18) Pipelined Sync SRAM
  • CY7C1214F - 1-Mb (32K x 32) Flow-Through Sync SRAM
  • CY7C1214H - 1-Mbit (32K x 32) Flow-Through Sync SRAM
  • CY7C1215F - 1-Mb (32K x 32) Pipelined Sync SRAM
  • CY7C1215H - 1-Mbit (32K x 32) Pipelined Sync SRAM
  • CY7C1217F - 1-Mbit (32K x 36) Flow-Through Sync SRAM
  • CY7C1217H - 1-Mbit (32K x 36) Flow-Through Sync SRAM

Full PDF Text Transcription

Click to expand full text
Features • Can support up to 117-MHz bus operations with zero wait states — Data is transferred on every clock w w • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through operation • Byte Write capability • 128K x 18 common I/O architecture • Single 3.3V power supply • Fast clock-to-output times — 7.5 ns (for 117-MHz device) — 8.5 ns (for 100-MHz device) • Clock Enable (CEN) pin to suspend operation • Synchronous self-timed writes • Asynchronous Output Enable • JEDEC-standard 100 TQFP package • Low standby power • Burst Capability—linear or interleaved burst order w .D at h S a ee U 4 t .
Published: |