CY7C1241KV18 architecture equivalent, 36-mbit qdr ii sram 4-word burst architecture.
* Configurations With Read Cycle Latency of 2.0 cycles: CY7C1241KV18 – 4 M × 8 CY7C1256KV18 – 4 M × 9 CY7C1243KV18 – .
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