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CY7C1245KV18 Datasheet 36-Mbit QDR II SRAM 4-Word Burst Architecture

Manufacturer: Cypress (now Infineon)

Overview: 36-Mbit QDR II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.

Download the CY7C1245KV18 datasheet PDF. This datasheet also includes the CY7C1241KV18 variant, as both parts are published together in a single manufacturer document.

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General Description

■ ■ ■ ■ ■ Functional Description The CY7C1241KV18, CY7C1256KV18, CY7C1243KV18, and CY7C1245KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II+ architecture.

Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array.

The read port has dedica

Key Features

  • Configurations With Read Cycle Latency of 2.0 cycles: CY7C1241KV18.
  • 4 M × 8 CY7C1256KV18.
  • 4 M × 9 CY7C1243KV18.
  • 2 M × 18 CY7C1245KV18.
  • 1 M × 36 Separate independent read and write data ports.
  • Supports concurrent transactions 450 MHz clock for high bandwidth 4-word burst for reducing address bus frequency Double data rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz Available in 2.0 clock cycle latency Two.

More Datasheets from Cypress (now Infineon)

Part Number Description
CY7C12451KV18 36-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C12411KV18 36-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1241KV18 36-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1241V18 36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C12431KV18 36-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1243KV18 36-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1243V18 36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1248KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture
CY7C1212F 1-Mbit (64K x 18) Pipelined Sync SRAM
CY7C1212H 1-Mbit (64K x 18) Pipelined Sync SRAM