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Cypress Semiconductor Electronic Components Datasheet

CY7C1355B Datasheet

(CY7C1355B / CY7C1357B) 9-Mb (256K x 36/512K x 18) Flow-Through SRAM

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CY7C1355B
CY7C1357B
9-Mb (256K x 36/512K x 18) Flow-Through
SRAM with NoBL™ Architecture
Features
• No Bus Latency™ (NoBL™) architecture eliminates
dead cycles between write and read cycles.
• Can support up to 133-MHz bus operations with zero
wait states
— Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 3.3V/2.5V I/O power supply
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
— 7.0 ns (for 117-MHz device)
— 7.5 ns (for 100-MHz device)
• Clock Enable (CEN) pin to enable clock and suspend
operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• Offered in JEDEC-standard 100 TQFP, 119-Ball BGA and
165-Ball fBGA packages
• Three chip enables for simple depth expansion.
• Automatic Power-down feature available using ZZ
mode or CE deselect.
• JTAG boundary scan for BGA and fBGA packages
• Burst Capability—linear or interleaved burst order
• Low standby power
Functional Description[1]
The CY7C1355B/CY7C1357B is a 3.3V, 256K x 36/ 512K x 18
Synchronous Flow-through Burst SRAM designed specifically
to support unlimited true back-to-back Read/Write operations
without the insertion of wait states. The
CY7C1355B/CY7C1357B is equipped with the advanced No
Bus Latency (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput
of data through the SRAM, especially in systems that require
frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two or four Byte Write
Select (BWX) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Selection Guide
133 MHz
117 MHz
100 MHz
Maximum Access Time
6.5 7.0 7.5
Maximum Operating Current
250 220 180
Maximum CMOS Standby Current 30 30 30
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Unit
ns
mA
mA
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05117 Rev. *B
Revised January 27, 2004
DataSheet4 U .com


Cypress Semiconductor Electronic Components Datasheet

CY7C1355B Datasheet

(CY7C1355B / CY7C1357B) 9-Mb (256K x 36/512K x 18) Flow-Through SRAM

No Preview Available !

www.DataSheet4U.com
CY7C1355B
CY7C1357B
1
Logic Block Diagram – CY7C1355B (256K x 36)
A0, A1, A
MODE
CLK C
CEN
CE
ADDRESS
REGISTER
A1
A0
D1
D0
ADV/LD
C
WRITE ADDRESS
REGISTER
Q1
Q0
A1'
A0'
BURST
LOGIC
ADV/LD
BWA
AB0W, AB 1, A
BWC
BWMDODE
CLK WEC
CEN
CE
WRITE REGISTRY
ADDRESS AND DATA COHERENCY
REGISTER
CONTROL LAAO01GDDIC10
Q1
Q0
A1'
A0'
BURST
ADV/LD
LOGIC
C
WRITE
DRIVERS
OE
CE1
CE2
CE3
ZZ
ADV/LD
WRITE ADDRESS
REGISTER
READ LOGIC
SLEEP
CONTROL
BWA WRITE REGISTRY
BWB AND DATA COHERENCY
2
Logic Block Diagram – CY7C1357CBON(T5RO1L2LOKGICx 18)
WRITE
DRIVERS
A0, A1, AWE
MODE
CLK C
CE
CEN
OE
CE1
CE2
CE3
ZZ
ADV/LD
BWA
BWB
ADDRESS
REGISTER
A1
A0
D1
D0
ADV/LD
C
RWEARIDTELOAGDICDRESS
REGISTER
Q1
Q0
A1'
A0'
BURST
LOGIC
SLEEP
CONTROL
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
WE
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
INPUT E
REGISTER
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
INPUT E
REGISTER
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
DP
AU
TT
A
B
SU
TF
EF
EE
RR
IS
NE
G
O
U
T
DP
AU
TT
A
B
SU
TF
EF
EE
RR
IS
NE
G
O
U
T
DP
AU
TT
A
B
SU
TF
EF
EE
RR
IS
NE
G
DQs
DQPA
DQPB
DQPC
DQPD
DQs
DQPA
DQPB
DQs
DQPA
DQPB
OE
CE1
READ LOGIC
CE2
CE3
ZZ
SLEEP
CONTROL
INPUT E
REGISTER
Document #: 38-05117 Rev. *B
Page 2 of 33
DataSheet4 U .com


Part Number CY7C1355B
Description (CY7C1355B / CY7C1357B) 9-Mb (256K x 36/512K x 18) Flow-Through SRAM
Maker Cypress Semiconductor
Total Page 30 Pages
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