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CY7C1386D Datasheet 18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM

Manufacturer: Cypress (now Infineon)

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General Description

The CY7C1386D/CY7C1387D SRAM integrates 512K × 36/1M × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation.

All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK).

The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth expansion chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and ADV), write enables (BWX, and BWE), and global write (GW).

Overview

Not Recommended for New Design CY7C1386D CY7C1387D 18-Mbit (512K × 36/1M × 18) Pipelined DCD Sync SRAM 18-Mbit (512K × 36/1M × 18) Pipelined DCD Sync.

Key Features

  • Supports bus operation up to 200 MHz.
  • Available speed grades are 200, and 167 MHz.
  • Registered inputs and outputs for pipelined operation.
  • Optimal for performance (double-cycle deselect).
  • Depth expansion without wait state.
  • 3.3 V core power supply (VDD).
  • 2.5 V or 3.3 V I/O power supply (VDDQ).
  • Fast clock-to-output times.
  • 3 ns (for 200 MHz device).
  • Provides high performance 3-1-1-1 access rate.
  • User selectable burst counter supporting Intel.

📁 Similar Datasheet

Brand Logo Part Number Description Manufacturer
Cypress Logo CY7C1386S 18-Mbit (512 K x 36) Pipelined DCD Sync SRAM Cypress

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