Download CY7C1420BV18 Datasheet PDF
CY7C1420BV18 page 2
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CY7C1420BV18 page 3
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CY7C1420BV18 Key Features

  • 4M x 8 CY7C1427BV18
  • 4M x 9 CY7C1418BV18
  • 2M x 18 CY7C1420BV18

CY7C1420BV18 Description

The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K.