Download the CY7C1420JV18 datasheet PDF.
This datasheet also covers the CY7C1418JV18 variant, as both devices belong to the same 36-mbit ddr-ii sram 2-word burst architecture family and are provided as variant models within a single manufacturer datasheet.
General Description
The CY7C1416JV18, CY7C1427JV18, CY7C1418JV18 and CY7C1420JV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture.
The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter.
Note: The manufacturer provides a single datasheet file (CY7C1418JV18_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.
Full PDF Text Transcription for CY7C1420JV18 (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
CY7C1420JV18. For precise diagrams, and layout, please refer to the original PDF.
Burst Architecture Features ■ ■ ■ ■ ■ Functional Description The CY7C1416JV18, CY7C1427JV18, CY7C1418JV18 and CY7C1420JV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided.
CY7C1420JV18 Datasheet
