* Separate independent read and write data ports
* Supports concurrent transactions
* 550 MHz clock for high bandwidth
* Four-word burst for reducing address bus frequency
* Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MH
CY7C2265KV18 Datasheet (631.21 KB)
CY7C2265KV18
Cypress Semiconductor
631.21 KB
36-mbit qdr ii+ sram four-word burst architecture.
CY7C2263KV18/CY7C2265KV18 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 36-Mbit QDR® II+ SRAM 4-Word Burst Arc.
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