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CY7C2265XV18 - 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture

Download the CY7C2265XV18 datasheet PDF (CY7C2263XV18 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for 36-mbit qdr ii+ xtreme sram four-word burst architecture.

Features

  • Separate independent read and write data ports.
  • Supports concurrent transactions.
  • 633 MHz clock for high bandwidth.
  • Four-word burst for reducing address bus frequency.
  • Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 1266 MHz) at 633 MHz.
  • Available in 2.5 clock cycle latency.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Echo clocks (CQ and CQ) simplify data capture in high-speed sy.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C2263XV18-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Cypress Semiconductor
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Full PDF Text Transcription

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CY7C2263XV18 CY7C2265XV18 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 633 MHz clock for high bandwidth ■ Four-word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 1266 MHz) at 633 MHz ■ Available in 2.
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