CY9A110A Datasheet | Cypress

Features 32-bit Arm Cortex-M3 Core - Processor version: r2p1 - Up to 40 MHz Frequency Operation - Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels - 24-bit System timer (Sys Tick): System timer for OS task management On-chip Memories [Flash memory] - Up to 512 Kbyte - Read cycle: 0 wait-cycle - Security function for code protection [SRAM] This Series contain a total of up to 32 Kbyte on-chip SRAM. On-chip SRAM is posed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and Dcode bus of Cortex-M3 core. SRAM1 is connected to System bus. - SRAM0: Up to 16 Kbytes - SRAM1: Up to 16 Kbytes Multi-function Serial Interface (Max 8 channels) - 4 channels with 16 steps×9bit FIFO (ch.4-ch.7), 4 channels without FIFO (ch.0-ch3) - Operation mode is selectable from the followings for each channel.  UART  CSIO  LIN  I2C [UART] - Full duplex double buffer - Selection with or without parity supported - Built-in dedicated baud rate generator - External clock available as a serial clock - Hardware Flow control: Automatically control the transmission by CTS/RTS (only ch.4)- - Various error detection functions available (parity errors, framing errors, and overrun errors) - : CY9AF111LA, F112LA, F114LA, F112L and F114L do not support Hardware Flow control [CSIO] - Full duplex double buffer - Built-in dedicated baud rate generator - Overrun error detection function available [LIN] - LIN protocol Rev.2.1 supported - Full duplex double buffer - Master/Slave mode supported - LIN break field generation (can be changed 13- 16bit length) - LIN break delimiter generation (can be changed 1 - 4bit length) - Various error detection functions available (parity errors, framing errors, and overrun errors) [I2C] Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported Cypress Semiconductor Corporation An Infineon Technologies pany Document Number: 002-04672...