CYB06445LQI-S3D42 Datasheet | Cypress

Description PSo C® 6 MCU is a high-performance, ultra-low-power and secured MCU platform, purpose-built for Io T applications. The PSo C 64 product line, based on the PSo C 6 MCU platform, Features out-of-box security functionality, providing an isolated root-of-trust with true attestation and provisioning services. In addition, it delivers a pre-configured secured execution environment which supports system software for various Io T platforms; and enables TLS authentication, secured storage, and secured firmware management. PSo C 64 also includes a rich execution environment for application development, with RTOS support that municates with the secured execution environment. Features 32-bit Dual CPU Subsystem Note: In PSo C 64 the Cortex M0+ is reserved for system functions, and is not available for applications. - 150-MHz Arm® Cortex®-M4F (CM4) CPU with single-cycle multiply, floating point, and memory protection unit (MPU) - 100-MHz Cortex-M0+ (CM0+) CPU with single-cycle multiply and MPU - User-selectable core logic operation at either 1.1 V or 0.9 V - Active CPU current slope with 1.1-V core operation - Cortex-M4: 40 µA/MHz - Cortex-M0+: 20 µA/MHz - Active CPU current slope with 0.9-V core operation - Cortex-M4: 22 µA/MHz - Cortex-M0+: 15 µA/MHz - Three DMA controllers Memory Subsystem - 384-KB application flash, 32-KB auxiliary flash (AUXflash), and 32-KB supervisory flash (SFlash); read-while-write (RWW) support. Two 8-KB flash caches, one for each CPU. - 176-KB SRAM with programmable power control and retention granularity - One-time-programmable (OTP) 1-Kb e Fuse array Hardware-Based Root-of-Trust (Ro T) - Ro T based on immutable boot-up code, flash content hash, and Cypress public key that ensures firmware integrity prior to provisioning - Supports trusted Ro T handover to maintain chain of trust and establish OEM trust anchor for secured boot - Device generates a unique device ID and a device secret key during the provisioning process, which can be used for...