CYD04S36V18
Key Features
- PROBLEM DEFINITION The 256-Ball FBGA package substrate design has the ZQ0L pin shorted to ZQ1L and ZQ0R shorted to ZQ1R. The ZQ1L and ZQ1R pins are not internally connected to the die for the affected devices; therefore, when resistors are connected to these pins to ground, the effective output driver impedance for each port is halved.
- PARAMETERS AFFECTED Effective output driver impedance controlled by the VIM circuitry.
- TRIGGER CONDITION(S) If the designer populates resistors for both ZQ0 and ZQ1, the short between ZQ0 and ZQ1 halves the effective impedance seen by the VIM calibrating circuitry.
- SCOPE OF IMPACT Output driver impedance is halved, as the two VIM calibrating resistors are in parallel to ground.
- WORKAROUND Remove ZQ1L and ZQ1R VIM resistors. Disconnecting these two resistors and leaving the pins open allow the calibrating circuitry to set the correct output driver impedance.
- FIX STATUS The date for the substrate design fix is TBD. References 1. Document # 38-06072, FullFlex Synchronous DDR Dual-Port SRAM 2. Document # 38-06082, FullFlex Synchronous SDR Dual-Port SRAM Cypress Semiconductor Corporation Document #: 001-07077 Rev. **
- 198 Champion Court
- San Jose, CA 95134-1709
- 408-943-2600 Revised March 28, 2006
