CYD04S36V18
Key Features
- PARAMETERS AFFECTED Effective output driver impedance controlled by the VIM circuitry
- SCOPE OF IMPACT Output driver impedance is halved, as the two VIM calibrating resistors are in parallel to ground
- FIX STATUS The date for the substrate design fix is TBD. References
- Document # 38-06072, FullFlex Synchronous DDR Dual-Port SRAM
- Document # 38-06082, FullFlex Synchronous SDR Dual-Port SRAM Cypress Semiconductor Corporation Document #: 001-07077 Rev. **
- 198 Champion Court
- San Jose, CA 95134-1709
