CYDXXS18V18 Key Features
- Functional Description
- True dual port memory enables simultaneous access the shared array from each port Synchronous pipelined operation with s
- SDR interface at 200 MHz
- 36-Mbit: 512 K × 72 (CYD36S72V18)
- 18-Mbit: 256 K × 72 (CYD18S72V18)
- 9-Mbit: 128 K × 72 (CYD09S72V18) FullFlex36 family
- 36-Mbit: 1 M × 36 (CYD36S36V18)
- 18-Mbit: 512 K × 36 (CYD18S36V18)
- 9-Mbit: 256 K × 36 (CYD09S36V18)
- 2-Mbit: 64 K × 36 (CYD02S36V18) FullFlex18 family