Datasheet4U Logo Datasheet4U.com

CYUSB2025 - USB and Mass Storage Peripheral Controller

Download the CYUSB2025 datasheet PDF (CYUSB2024 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for usb and mass storage peripheral controller.

Features

  • Latest-generation storage support.
  • SD2.0/SDXC.
  • UHS1 SDR50 / DDR50 Master.
  • eMMC 4.4 Master.
  • SDIO 3.0 Master.
  • USB integration.
  • Certified USB 2.0 peripheral: Hi-Speed (HS), and Full-Speed (FS) only).
  • Thirty-two physical endpoints.
  • Integrated transceiver.
  • Accessory charger adaptor (ACA) support.
  • Ultra low-power in core power-down mode.
  • Less than 60 µA with VBATT on and 20 µA with VBATT off.
  • I2C master controller at 1 MHz.
  • Se.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CYUSB2024-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

  • CYUSB2014 - SuperSpeed USB Controller (Infineon)
  • CYUSB3011 - SuperSpeed USB Controller (Cypress)
  • CYUSB3011 - SuperSpeed USB Controller (Infineon)
  • CYUSB3012 - SuperSpeed USB Controller (Cypress)
  • CYUSB3012 - SuperSpeed USB Controller (Infineon)
  • CYUSB3013 - SuperSpeed USB Controller (Cypress)
  • CYUSB3013 - SuperSpeed USB Controller (Infineon)
  • CYUSB3014 - SuperSpeed USB Controller (Cypress)
  • CYUSB3014 - SuperSpeed USB Controller (Infineon)
  • CYUSB3015 - Configurable SuperSpeed USB Controller (Cypress)
Other Datasheets by Cypress Semiconductor

Full PDF Text Transcription

Click to expand full text
CYUSB202X SD2™ USB and Mass Storage Peripheral Controller Features ■ Latest-generation storage support ❐ SD2.0/SDXC – UHS1 SDR50 / DDR50 Master ❐ eMMC 4.4 Master ❐ SDIO 3.0 Master ■ USB integration ❐ Certified USB 2.0 peripheral: Hi-Speed (HS), and Full-Speed (FS) only) ❐ Thirty-two physical endpoints ❐ Integrated transceiver ❐ Accessory charger adaptor (ACA) support ■ Ultra low-power in core power-down mode ❐ Less than 60 µA with VBATT on and 20 µA with VBATT off ■ I2C master controller at 1 MHz ■ Selectable input clock frequencies ❐ 19.2, 26, 38.4, and 52 MHz ❐ 19.2-MHz crystal input support ■ Independent power domains for core and I/O ■ 10 × 10 mm, 0.
Published: |