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Cypress Semiconductor Electronic Components Datasheet

CYW43143 Datasheet

Single Chip IEEE 802.11 b/g/n MAC/PHY/Radio

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ADVANCE
CYW43143
Single Chip IEEE 802.11 b/g/n MAC/PHY/Radio with
USB/SDIO Host Interface
The CYW43143 is a single-band, single-stream, IEEE 802.11n compliant, MAC/PHY/Radio system-on-a-chip with internal 2.4 GHz
Power Amplifier (PA) and integrated T/R switch. The CYW43143 supports internal RX diversity by providing two antenna ports. The
device enables development of USB or SDIO 802.11n WLAN clients that can take advantage of the high throughput and extended
range of Cypress second-generation solution. The CYW43143 maintains compatibility with legacy IEEE 802.11b/g devices.
State-of-the-art security is provided by industry standard support for WPA, WPA2 (802.11i), and hardware-accelerated AES
encryption/decryption, coupled with TKIP, IEEE 802.1X support, and a WLAN Authentication and Privacy Infrastructure (WAPI)
hardware engine.
Embedded hardware acceleration enables increased system performance and reduced host-CPU utilization in both client and access
point configurations. The CYW43143 also supports Cypress widely accepted and deployed WPS to easily secure WLAN networks.
SDIO and USB wireless client modules for digital TVs, Blu-ray Disc® players, set-top boxes, game consoles, and printers.
Supports the I2S digital audio interface.
Stand-alone wireless USB dongles and multimedia streaming boxes.
Cypress Part Numbering Scheme
Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion,
there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides
Cypress ordering part number that matches an existing IoT part number.
Table 1. Mapping Table for Part Number between Broadcom and Cypress
Broadcom Part Number
BCM43143
BCM43143KMLG
Cypress Part Number
CYW43143
CYW43143KMLG
Features
Supports 3.3V ±10% power supply input with high efficiency
Power Management Unit (PMU).
Programmable dynamic power management.
Eight GPIOs with multiplexed JTAG interface.
Complies with USB 2.0 specification and link power
management.
Supports standard SDIO v2.0 (50 MHz, 4-bit and 1-bit) and
USB host interfaces.
20 MHz reference clock.
IEEE 802.11x Key Features:
IEEE 802.11n compliant.
2.4 GHz internal PA.
Internal T/R and RX diversity switches.
Supports MCS 0–7 coding rates.
Support for Short Guard Interval (SGI).
Supports USB 2.0, standard SDIO v2.0 (50 MHz,
4-bit and 1-bit) host interfaces.
Supports the I2S audio interface.
Greenfield, mixed mode, and legacy mode support.
802.11n MPDU/MSDU aggregation support for high
throughput.
Full IEEE 802.11b/g legacy compatibility with enhanced perfor-
mance.
Supports Cypress OneDriver™ software.
Supports drivers for Windows®, Linux®, and Android™
operating systems.
Comprehensive wireless network security support that
includes WPA, WPA2, and AES encryption/decryption, coupled
with TKIP, IEEE 802.1X support, and a WAPI encryption/
decryption engine.
Single stream IEEE 802.11n support for 20 MHz and 40 MHz
channels provides PHY layer rates up to 150 Mbps for typical
upper-layer throughput in excess of 90 Mbps.
Supports the IEEE 802.11n RX space-time block coding
(STBC) and low-density parity check (LDPC) options for
improved range and power efficiency.
Supports an IEEE 802.15.2 external coexistence interface to
optimize bandwidth utilization with other colocated wireless
technologies such as GPS, WiMAX, LTE, Bluetooth, and UWB.
Integrated ARM Cortex-M3 processor and on-chip memory for
complete WLAN subsystem functionality, minimizing the need
to wake up the applications processor for standard WLAN
functions. This allows for further minimization of power
consumption while maintaining the ability to field upgrade with
future features. On-chip memory includes 448 KB SRAM and
256 KB ROM.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-15045 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 20, 2017


Cypress Semiconductor Electronic Components Datasheet

CYW43143 Datasheet

Single Chip IEEE 802.11 b/g/n MAC/PHY/Radio

No Preview Available !

ADVANCE
CYW43143
USB 2.0 with Link Power Management (LPM) for low power
standby application.
SDIO out of band low power application.
Integrated One Time Programmable (OTP) memory to save
configuration settings.
Single stream IEEE 802.11n support for 20 MHz and 40 MHz
channels provides PHY layer rates up to 150 Mbps for typical
upper-layer throughput in excess of 90 Mbps.
Supports the IEEE 802.11n RX space-time block coding
(STBC) and low-density parity check (LDPC) options for
improved range and power efficiency.
Package options:
7 mm × 7 mm, 56-pin QFN package.
Figure 1.CYW43143 High-Level Block Diagram
JTAG
USB
SDIO or I2S 
Interface
GPIO
JTAG
USB 2.0 
Device
SDIO or 
I2S 
Interface
GPIO
CYW43143
IEEE 
802.11n 
MAC
IEEE 
802.11n 
PHY
IEEE 
802.11n
2.4 GHz 
Radio
Security
OTP
(2 Kbits)
Serial 
Flash 
Interface
PA
2.4 GHz
RF Front 
End 
(switches)
FLASH 
Memory
IoT Resources
Cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for your
design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of
information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software
updates. Customers can acquire technical documentation and software from the Cypress Support Community website
(http://community.cypress.com/).
Document Number: 002-15045 Rev. *F
Page 2 of 44


Part Number CYW43143
Description Single Chip IEEE 802.11 b/g/n MAC/PHY/Radio
Maker Cypress Semiconductor
Total Page 30 Pages
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