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GVT7C1360A - 256K x 36 / 512K x 18 Pipelined SRAM

This page provides the datasheet information for the GVT7C1360A, a member of the GVT71256D36 256K x 36 / 512K x 18 Pipelined SRAM family.

Datasheet Summary

Description

The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology.

Each memory cell consists of four transistors and two high-valued resistors.

Features

  • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns Fast clock speed: 225, 200, 166, and 150 MHz Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns Optimal for depth expansion (one cycle chip deselect to eliminate bus contention) 3.3V.
  • 5% and +10% power supply 3.3V or 2.5V I/O supply 5V tolerant inputs except I/Os Clam.

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Datasheet preview – GVT7C1360A

Datasheet Details

Part number GVT7C1360A
Manufacturer Cypress Semiconductor
File Size 793.06 KB
Description 256K x 36 / 512K x 18 Pipelined SRAM
Datasheet download datasheet GVT7C1360A Datasheet
Additional preview pages of the GVT7C1360A datasheet.

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Full PDF Text Transcription

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( DataSheet : www.DataSheet4U.com ) 1CY7C1329 PRELIMINARY CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 256K x 36/512K x 18 Pipelined SRAM Features • • • • • • • • • • • • • • • • • • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns Fast clock speed: 225, 200, 166, and 150 MHz Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns Optimal for depth expansion (one cycle chip deselect to eliminate bus contention) 3.3V –5% and +10% power supply 3.3V or 2.
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