GVT7C1361A
Key Features
- All synchronous inputs are gated by registers controlled by a positiveedge-triggered Clock Input (CLK)
- However, the CE2 chip enable input is only available for TA(GVTI)/A(CY) package version
- Asynchronous inputs include the Output Enable (OE) and burst mode control (MODE)
- The data outputs (Q), enabled by OE, are also asynchronous
- Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address Status Controller (ADSC) input pins
- Subsequent burst addresses can be internally generated as controlled by the Burst Advance pin (ADV)
- Address, data inputs, and write controls are registered on-chip to initiate self-timed WRITE cycle
- WRITE cycles can be one to four bytes wide as controlled by the write control inputs
- Individual byte write allows individual byte to be written
- BWa, BWb, BWc, and BWd can be active only with BWE being LOW
