24, 23, 22, 19, 18 CLK(0:4)
10*, 11*, 12*
5, 9, 16, 21, 26
Crystal Buffer Input Pin. Connects to a crystal, or an external clock
source. Serves as input clock TCLK, in Test mode.
Crystal Buffer Output Pin. Connects to a crystal only. When a Can
Oscillator is used or in test mode, this pin is kept unconnected.
Buffered inverted outputs of the signal applied at Xin, typically
33.33 or 25.0 MHz.
Output Enable for Clock Bank. Causes the CLK (0:4) output clocks
to be in a three-state condition when driven to a logic low level.
A bank of five XINx1, XINx2, XINx3 and XINx4 output clocks.
When his output signal is a logic low level, it indicates that the output
clocks of the bank are locked to the input reference clock. This
output is latched.
Clock Bank Selection Bits. These control the clock frequency that will
be present on the outputs of the bank of buffers. See table on page
one for frequency codes and selection values.
3.3V common power supply pin for all PCI clocks CLK (0:4).
SMBus Address Selection Input Pins. See Table 3 on page 3.
Spread Spectrum Clock Generator. Enables Spread Spectrum clock
modulation when at a logic low level, see Spread Spectrum Clocking
on page 6.
Data for the Internal SMBus Circuitry. See Table 3 on page 3.
Clock for the Internal SMBus Circuitry. See Table 3 on page 3.
Power for Internal Analog Circuitry. This supply should have a
separately decoupled current source from VDD.
Power supply for internal core logic.
Ground pins for the device.
2. Pin numbers ending with * indicate that they contain device internal pull-up resistors that will insure that they are sensed as a logic 1 if no external circuitry is
connected to them.
3. A bypass capacitor (0.1µF) should be placed as close as possible to each VDD pin. If these bypass capacitors are not close to the pins their high frequency
filtering characteristic will be cancelled by the lead inductance of the trace.
4. PWR = Power connection, I = Input, O = Output and I/O = both input and output functionality of the pin(s).
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
The clock driver serial protocol accepts block write a opera-
tions from the controller. The bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. The C9531 does not support the Block Read
The block write protocol is outlined in Table 2. The addresses
are listed in Table 3.
Document #: 38-07034 Rev. *D
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