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Cypress Semiconductor Electronic Components Datasheet

MB9BF568R Datasheet

Microcontroller

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MB9B560R Series
32-Bit ARM® Cortex® - M4F
FM4 Microcontroller
Devices in the MB9B560R Series are highly integrated 32-bit microcontrollers with high performance and competitive cost.
This series is based on the ARM® Cortex®-M4F Processor with on-chip Flash memory and SRAM. The series has peripheral
functions such as Motor Control Timers, ADCs and Communication Interfaces (USB, CAN, UART, CSIO, I2C, LIN).
Features
32-bit ARM® Cortex®-M4F Core
Processor version: r0p1
Up to 160 MHz Frequency Operation
FPU built-in
Support DSP instruction
Memory Protection Unit (MPU): improves the reliability of an
embedded system
Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 128 peripheral interrupts
and 16 priority levels
24-bit System timer (Sys Tick): System timer for OS task
management
On-chip Memories
Flash memory
These series are based on two independent on-chip Flash
memories.
MainFlash memory
Up to 1024 Kbytes
Built-in Flash Accelerator System with 16 Kbytes trace
buffer memory
The read access to Flash memory can be achieved
without wait-cycle up to operation frequency of 72 MHz.
Even at the operation frequency more than 72 MHz, an
equivalent access to Flash memory can be obtained by
Flash Accelerator System.
Security function for code protection
WorkFlash memory
32 Kbytes
Read cycle:
6wait-cycle: the operation frequency more than 120 MHz,
and up to 160 MHz
4wait-cycle: the operation frequency more than 72 MHz,
and up to 120 MHz
2wait-cycle: the operation frequency more than 40 MHz,
and up to 72 MHz
0wait-cycle: the operation frequency up to 40 MHz
Security function is shared with code protection
SRAM
This is composed of three independent SRAMs (SRAM0,
SRAM1, and SRAM2). SRAM0 is connected to I-code bus and
D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are
connected to System bus of Cortex-M4F core.
SRAM0: Up to 64 Kbytes
SRAM1: Up to 32 Kbytes
SRAM2: Up to 32 Kbytes
External Bus Interface
Supports SRAM, NOR, NAND Flash, and SDRAM device
Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM)
8-/16-bit Data width
Up to 25-bit Address bit
Supports Address/Data multiplex
Supports external RDY function
Supports scramble function
Possible to set the validity/invalidity of the scramble
function for the external areas 0x6000_0000 to
0xDFFF_FFFF in 4 Mbytes units.
Possible to set two kinds of the scramble key
Note:
It is necessary to prepare the dedicated software library
to use the scramble function.
USB Interface
USB interface is composed of Function and Host.
[USB function]
USB2.0 Full-Speed supported
Max 6 Endpoint supported
Endpoint 0 is control transfer
Endpoint 1, 2 can be selected Bulk-transfer,
Interrupt-transfer or Isochronous-transfer
Endpoint 3 to 5 can select Bulk-transfer or
Interrupt-transfer
Endpoint 1 to 5 comprise Double Buffer
The size of each endpoint is according to the follows.
Endpoint 0, 2 to 5: 64 bytes
Endpoint 1: 256 bytes
Cypress Semiconductor Corporation
Document Number: 002-04864 Rev.*A
• 198 Champion Court • San Jose, CA 95134-1709
408-943-2600
Revised March 3, 2016


Cypress Semiconductor Electronic Components Datasheet

MB9BF568R Datasheet

Microcontroller

No Preview Available !

MB9B560R Series
[USB host]
USB2.0 Full/Low-speed supported
Bulk-transfer, interrupt-transfer and Isochronous-transfer
support
USB Device connected/dis-connected automatically detect
IN/OUT token handshake packet automatically
Max 256-byte packet-length supported
Wake-up function supported
CAN Interface (Max two channels)
Compatible with CAN Specification 2.0A/B
Maximum transfer rate: 1 Mbps
Built-in 32 message buffer
Multi-function Serial Interface (Max eight channels)
64 bytes with FIFO (the FIFO step numbers are variable
depending on the settings of the communication mode or bit
length.)
Operation mode is selectable from the followings for each
channel.
UART
CSIO
LIN
I2C
UART
Full-duplex double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Hardware Flow control : Automatically control the
transmission by CTS/RTS (only ch.4)
Various error detect functions available (parity errors,
framing errors, and overrun errors)
CSIO
Full-duplex double buffer
Built-in dedicated baud rate generator
Overrun error detect function available
Serial chip select function (ch.6 and ch.7 only)
Supports high-speed SPI (ch.4 and ch.6 only)
Data length 5 to 16-bit
LIN
LIN protocol Rev.2.1 supported
Full-duplex double buffer
Master/Slave mode supported
LIN break field generation (can change to 13 to 16-bit
length)
LIN break delimiter generation (can change to 1 to 4-bit
length)
Various error detect functions available (parity errors,
framing errors, and overrun errors)
I2C
Standard mode (Max 100 kbps) / High-speed mode (Max
400 kbps) supported
Fast mode Plus (Fm+) (Max 1000 kbps, only for ch.3=ch.A
and ch.7=ch.B) supported
DMA Controller (Eight channels)
DMA Controller has an independent bus for CPU, so CPU and
DMA Controller can process simultaneously.
8 independently configured and operated channels
Transfer can be started by software or request from the
built-in peripherals
Transfer address area: 32-bit (4 Gbytes)
Transfer mode: Block transfer/Burst transfer/Demand
transfer
Transfer data type: bytes/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
DSTC (Descriptor System data Transfer Controller)
(128 channels)
The DSTC can transfer data at high-speed without going via
the CPU. The DSTC adopts the Descriptor system and,
following the specified contents of the Descriptor which has
already been constructed on the memory, can access directly
the memory /peripheral device and performs the data transfer
operation.
It supports the software activation, the hardware activation and
the chain activation functions.
A/D Converter (Max 24 channels)
[12-bit A/D Converter]
Successive Approximation type
Built-in 3 units
Conversion time: 0.5 μs @ 5 V
Priority conversion available (priority at 2levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN
conversion: 16steps, for Priority conversion: 4steps)
DA Converter (Max two channels)
R-2R type
12-bit resolution
Document Number: 002-04864 Rev.*A
Page 2 of 169


Part Number MB9BF568R
Description Microcontroller
Maker Cypress Semiconductor
Total Page 30 Pages
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