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Cypress Semiconductor Electronic Components Datasheet

PALCE16V8 Datasheet

Reprogrammable CMOS PAL Device

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16V8
PALCE16V8
Flash Erasable,
Reprogrammable CMOS PAL® Device
Features
• Active pull-up on data input pins
• Low power version (16V8L)
— 55 mA max. commercial (10, 15, 25 ns)
— 65 mA max. industrial (10, 15, 25 ns)
— 65 mA military (15 and 25 ns)
• Standard version has low power
— 90 mA max. commercial (10, 15, 25 ns)
— 115 mA max. commercial (7 ns)
— 130 mA max. military/industrial (10, 15, 25 ns)
• CMOS Flash technology for electrical erasability and
reprogrammability
• PCI compliant
• User-programmable macrocell
— Output polarity control
— Individually selectable for registered or combinato-
rial operation
• Up to 16 input terms and 8 outputs
7.5 ns coml version
5 ns tCO
5 ns tS
7.5 ns tPD
125-MHz state machine
10 ns military/industrial versions
7 ns tCO
10 ns tS
10 ns tPD
62-MHz state machine
High reliability
Proven Flash technology
100% programming and functional testing
Functional Description
The Cypress PALCE16V8 is a CMOS Flash Electrical Eras-
able second-generation programmable array logic device. It is
implemented with the familiar sum-of-product (AND-OR) logic
structure and the programmable macrocell.
Logic Block Diagram (PDIP/CDIP)
GND
I8
I7 I6
I5 I4
I3 I2 I1 CLK/I0
10 9 8 7 6 5 4 3 2 1
88
PROGRAMMABLE
AND ARRAY
(64 x 32)
88
8
88
8
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
11 12
OE/I9
I/O0
Pin Configurations
13 14 15 16
I/O1 I/O2 I/O3 I/O4
CLK/I0
I1
I2
I3
I4
I5
I6
I7
I8
GND
DIP
Top View
1 20
2 19
3 18
4 17
5 16
6 15
7 14
8 13
9 12
10 11
VCC
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
OE/I9
16V82
17 18
I/O5 I/O6
PLCC/LCC
Top View
19
I/O7
20
VCC 16V81
3 2 1 2019
I3 4
18
I4 5
17
I5 6
16
I6 7
15
I7 8
14
9 10111213
I/O6
I/O5
I/O4
I/O3
I/O2
16V83
Cypress Semiconductor Corporation 3901 North First Street San Jose CA 95134 408-943-2600
Document #: 38-03025 Rev. **
Revised September 3, 1998


Cypress Semiconductor Electronic Components Datasheet

PALCE16V8 Datasheet

Reprogrammable CMOS PAL Device

No Preview Available !

PALCE16V8
Selection Guide
tPD ns
Generic Part Number Coml/Ind Mil
PALCE16V8-5
5
PALCE16V8-7
7.5
PALCE16V8-10
10 10
PALCE16V8-15
15 15
PALCE16V8-25
25 25
PALCE16V8L-15
15 15
PALCE16V8L-25
25 25
Shaded area contains preliminary information.
tS ns
Coml/Ind Mil
3
7
10 10
12 12
15 20
12 12
15 20
tCO ns
Coml/Ind Mil
4
5
7 10
10 10
12 12
10 12
12 20
ICC mA
Coml Mil/Ind
115
115
90 130
90 130
90 130
55 65
55 65
Functional Description (continued)
The PALCE16V8 is executed in a 20-pin 300-mil molded DIP,
a 300-mil cerdip, a 20-lead square ceramic leadless chip car-
rier, and a 20-lead square plastic leaded chip carrier.
The device provides up to 16 inputs and 8 outputs. The
PALCE16V8 can be electrically erased and reprogrammed.
The programmable macrocell enables the device to function
as a superset to the familiar 20-pin PLDs such as 16L8, 16R8,
16R6, and 16R4.
The PALCE16V8 features 8 product terms per output and 32
input terms into the AND array. The first product term in a mac-
rocell can be used either as an internal output enable control
or as a data product term.
There are a total of 18 architecture bits in the PALCE16V8
macrocell; two are global bits that apply to all macrocells and
16 that apply locally, two bits per macrocell. The architecture
bits determine whether the macrocell functions as a register or
combinatorial with inverting or noninverting output. The output
enable control can come from an external pin or internally from
a product term. The output can also be permanently enabled,
functioning as a dedicated output or permanently disabled,
functioning as a dedicated input. Feedback paths are select-
able from either the input/output pin associated with the mac-
rocell, the input/output pin associated with an adjacent pin, or
from the macrocell register itself.
Power-Up Reset
All registers in the PALCE16V8 power-up to a logic LOW for
predictable system initialization. For each register, the associ-
ated output pin will be HIGH due to active-LOW outputs.
Electronic Signature
An electronic signature word is provided in the PALCE16V8
that consists of 64 bits of programmable memory that can con-
tain user-defined data.
Security Bit
A security bit is provided that defeats the readback of the in-
ternal programmed pattern when the bit is programmed.
Low Power
The Cypress PALCE16V8 provides low-power operation
through the use of CMOS technology, and increased testability
with Flash reprogrammability.
Product Term Disable
Product Term Disable (PTD) fuses are included for each prod-
uct term. The PTD fuses allow each product term to be individ-
ually disabled.
Configuration Table
CG0
0
0
1
1
1
CG1
CL0x
Cell Configuration
1 0 Registered Output
1 1 Combinatorial I/O
0 0 Combinatorial Output
0 1 Input
1 1 Combinatorial I/O
Devices Emulated
Registered Med PALs
Registered Med PALs
Small PALs
Small PALs
16L8 only
Document #: 38-03025 Rev. **
Page 2 of 13


Part Number PALCE16V8
Description Reprogrammable CMOS PAL Device
Maker Cypress Semiconductor
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PALCE16V8 Datasheet PDF





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