PALCE20V8 Datasheet | Cypress

20V8 Flash Erasable, Reprogrammable CMOS PAL Device Features - Active pull-up on data input pins - Low power version (20V8L) - 55 m A max. mercial (15, 25 ns) - 65 m A max. military/industrial (15, 25 ns) - Standard version has low power - 90 m A max. mercial (15, 25 ns) - 115 m A max. mercial (10 ns) - 130 m A max. military/industrial (15, 25 ns) - CMOS Flash technology for electrical erasability and reprogrammability - User-programmable macrocell - Output polarity control - Individually selectable for registered or binatorial operation - QSOP package available - 10, 15, and 25 ns ’l version - 15, and 25 ns military/industrial versions - High reliability - Proven Flash technology - 100% programming and functional testing Functional Description The Cypress PALCE20V8 is a CMOS Flash Erasable second-generation programmable array logic device. It is implemented with the familiar sum-of-product (AND-OR) logic structure and the programmable macrocell. The PALCE20V8 is executed in a 24-pin 300-mil molded DIP, a 300-mil cerdip, a 28-lead square ceramic leadless chip carrier, a 28-lead square plastic leaded chip carrier, and a 24-lead quarter size outline. The device provides up to 20 inputs and 8 outputs. The PALCE20V8 can be electrically erased and reprogrammed. The programmable macrocell enables the device to function as a superset to the familiar 24-pin PLDs such as 20L8, 20R8, 20R6, 20R4. Logic Block Diagram (PDIP/CDIP/QSOP) GND 12 I10 11 I9 10 I8 9 I7 8 I6 7 I5 6 I4 5 I3 4 I2 3 I1 2 CLK/I0 1 PROGRAMMABLE AND ARRAY (64 x 40) 8 8 8 8 8 8 8 8 Macrocell Macrocell Macrocell Macrocell...