PSoC4200
Overview
PSoC® 4 is a scalable and reconfigurable platform architecture for a family of mixed-signal programmable embedded system controllers with an Arm® Cortex™-M0 CPU, while being AEC-Q100 compliant. It combines programmable and re-configurable analog and digital blocks with flexible automatic routing.
- Automotive Electronics Council (AEC) AEC-Q100 qualified
- 48 MHz Arm Cortex-M0 CPU with single cycle multiply
- Up to 32 kB of flash with Read Accelerator
- Up to 4 kB of SRAM Programmable Analog
- One opamp with reconfigurable high-drive external and high-bandwidth internal drive, Comparator mode, and ADC input buffering capability
- 12-bit, 1-Msps SAR ADC with differential and single-ended modes; Channel Sequencer with signal averaging
- Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin
- Two low-power comparators that operate in Deep Sleep Programmable Digital
- Four programmable logic blocks called universal digital blocks, (UDBs), each with 8 Macrocells and data path
- Cypress-provided peripheral component library, user-defined state machines, and Verilog input Low Power 1.71 to 5.5 V operation
