S26KL512S - high-speed CMOS MirrorBit NOR flash devices

Cypress Semiconductor

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Datasheet Details

Part number	S26KL512S
Manufacturer	Cypress Semiconductor
File Size	1.67 MB
Description	high-speed CMOS MirrorBit NOR flash devices
Datasheet	S26KL512S-CypressSemiconductor.pdf

S26KL512S Product details

Description

4 1.1 DDR Center Aligned Read Strobe Functionality (DCARS) 6 1.2 Error Detection and Correction Functionality 6 2. Connection Diagram 9 2.1 FBGA 24-Ball 5 x 5 Array Footprint 9 3. Signal Description 10 4. HyperBus Protocol 11 4.1 Command / Address Bit Assignments 11 4.2 Read Operations 12 4.3 HyperFlash Read with DCARS Timing 15 4.4 Write Operations 16 5. Address Space Maps 18 5.1 Flash Memory Array 19 5.2 Device ID and CFI (ID-CFI) ASO 21 6. Embedded Operations 23 6.1 Embedded Algorith

Features

3.0V I/O, 11 bus signals.
Single ended clock.
1.8V I/O, 12 bus signals.
Differential clock (CK, CK#).
Chip Select (CS#).
8-bit data bus (DQ[7:0]).
Read-Write Data Strobe (RWDS).
HyperFlash™ memories use RWDS only as a Read Data Strobe.
Up to 333 MBps sustained read throughput.
DDR.
two data transfers per clock.
166-MHz clock rate (333 MBps) at 1.8V VCC.
100-MHz clock rate (200 MBps) at 3.0V VCC.
96-ns initial random read.

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Published: Dec 9, 2016 |