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Cypress Semiconductor Electronic Components Datasheet

S26KS512S Datasheet

high-speed CMOS MirrorBit NOR flash devices

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S26KL512S/S26KS512S
S26KL256S/S26KS256S
S26KL128S/S26KS128S
512 Mb (64 MB)/256 Mb (32 MB)/
128 Mb (16 MB), 1.8V/3.0V
HyperFlash™ Family
Features
3.0V I/O, 11 bus signals
Single ended clock
1.8V I/O, 12 bus signals
Differential clock (CK, CK#)
Chip Select (CS#)
8-bit data bus (DQ[7:0])
Read-Write Data Strobe (RWDS)
HyperFlash™ memories use RWDS only as a Read Data
Strobe
Up to 333 MBps sustained read throughput
DDR – two data transfers per clock
166-MHz clock rate (333 MBps) at 1.8V VCC
100-MHz clock rate (200 MBps) at 3.0V VCC
96-ns initial random read access time
Initial random access read latency: 5 to 16 clock cycles
Sequential burst transactions
Configurable Burst Characteristics
Wrapped burst lengths:
• 16 bytes (8 clocks)
• 32 bytes (16 clocks)
• 64 bytes (32 clocks)
Linear burst
Hybrid option: one wrapped burst followed by linear burst
Wrapped or linear burst type selected in each transaction
Configurable output drive strength
Low Power Modes
Active Clock Stop During Read: 12 mA, no wake-up required
Standby: 25 µA (typical), no wake-up required
Deep Power-Down: 8 µA (typical)
• 300 µs wake-up required
INT# output to generate external interrupt
Busy to Ready Transition
ECC detection
RSTO# output to generate system level power-on reset
User configurable RSTO# Low period
512-byte Program Buffer
Sector Erase
Uniform 256-KB sectors
Optional Eight 4-KB Parameter Sectors (32 KB total)
Advanced Sector Protection
Volatile and Nonvolatile protection methods for each sector
Separate 1024-byte one-time program array
Operating Temperature
Industrial (–40°C to +85°C)
Industrial Plus (–40°C to +105°C)
Extended (–40°C to +125°C)
Automotive, AEC-Q100 Grade 3 (–40°C to +85°C)
Automotive, AEC-Q100 Grade 2 (–40°C to +105°C)
Automotive, AEC-Q100 Grade 1 (–40°C to +125°C)
ISO/TS16949 and AEC Q100 Certified
Endurance
100,000 program/erase cycles
Retention
20 year data retention
Erase and Program Current
Max Peak 100 mA
Packaging Options
24-Ball FBGA
Additional Features
ECC 1-bit correction, 2-bit detection
CRC
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-99198 Rev. *M
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 12, 2019


Cypress Semiconductor Electronic Components Datasheet

S26KS512S Datasheet

high-speed CMOS MirrorBit NOR flash devices

No Preview Available !

Performance Summary
Read Access Timings
Maximum Clock Rate at 1.8V VCC/VCCQ
Maximum Clock Rate at 3.0V VCC/VCCQ
Maximum Access Time, (tACC)
Maximum CS# Access Time to First Word @ 166 MHz
Typical Program / Erase Times
Single Word Programming (2B = 16b)
Write Buffer Programming (512B = 4096b)
Sector Erase Time (256 KB = 2 Mb)
Typical Current Consumption
Burst Read (Continuous Read at 166 MHz)
Power-On Reset
Sector Erase Current
Write Buffer Programming Current
Standby (CS# = High)
Deep Power-Down (CS# = High, 85°C)
S26KL512S/S26KS512S
S26KL256S/S26KS256S
S26KL128S/S26KS128S
166 MHz
100 MHz
96 ns
118 ns
500 µs (~4 KBps)
475 µs (~1 MBps)
930 ms (~282 KBps)
80 mA
80 mA
60 mA
60 mA
25 µA
30 µA (512 Mb)
4 µA (all other densities)
Document Number: 001-99198 Rev. *M
Page 2 of 101


Part Number S26KS512S
Description high-speed CMOS MirrorBit NOR flash devices
Maker Cypress Semiconductor
Total Page 30 Pages
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