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Cypress Semiconductor Electronic Components Datasheet

S27KL0641 Datasheet

Self-Refresh DRAM

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S27KL0641/S27KS0641
S70KL1281/S70KS1281
3.0 V/1.8 V, 64 Mb (8 MB)/128 Mb (16 MB),
HyperRAM™ Self-Refresh DRAM
Distinctive Characteristics
HyperRAM™ Low Signal Count Interface
3.0 V I/O, 11 bus signals
Single ended clock (CK)
1.8 V I/O, 12 bus signals
Differential clock (CK, CK#)
Chip Select (CS#)
8-bit data bus (DQ[7:0])
Read-Write Data Strobe (RWDS)
Bidirectional Data Strobe / Mask
Output at the start of all transactions to indicate refresh la-
tency
Output during read transactions as Read Data Strobe
Input during write transactions as Write Data Mask
RWDS DCARS Timing
During read transactions RWDS is offset by a second clock,
phase shifted from CK
The Phase Shifted Clock is used to move the RWDS transi-
tion edge within the read data eye
High Performance
Up to 333 MBps
Double-Data Rate (DDR) - two data transfers per clock
166 MHz clock rate (333 MBps) at 1.8 V VCC
100 MHz clock rate (200 MBps) at 3.0 V VCC
Sequential burst transactions
Configurable Burst Characteristics
Wrapped burst lengths:
• 16 bytes (8 clocks)
• 32 bytes (16 clocks)
• 64 bytes (32 clocks)
• 128 bytes (64 clocks)
Linear burst
Hybrid option - one wrapped burst followed by linear burst
Wrapped or linear burst type selected in each transaction
Configurable output drive strength
Low Power Modes
Deep Power Down
Package
24-ball FBGA
Performance Summary
Maximum Clock Rate at 1.8 V VCC/VCCQ
Maximum Clock Rate at 3.0 V VCC/VCCQ
Maximum Access Time, (tACC at 166 MHz)
Maximum CS# Access Time to first word at
166 MHz (excluding refresh latency)
Read Transaction Timings
166 MHz
100 MHz
36 ns
56 ns
Maximum Current Consumption
Burst Read or Write (linear burst at 166 MHz, 1.8 V)
Power On Reset
Standby (CS# = HIGH, 3.0 V, 105 °C)
Deep Power Down (CS# = HIGH, 3.0 V, 105 °C)
Standby (CS# = HIGH, 1.8 V, 105 °C)
Deep Power Down (CS# = HIGH, 1.8 V, 105 °C)
64 MB
60 mA
50 mA
300 µA
40 µA
300 µA
20 µA
128 MB
72 mA
100 mA
600 µA
N/A
600 µA
N/A
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-97964 Rev. *L
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 31, 2018


Cypress Semiconductor Electronic Components Datasheet

S27KL0641 Datasheet

Self-Refresh DRAM

No Preview Available !

S27KL0641/S27KS0641
S70KL1281/S70KS1281
Logic Block Diagrams
Block Diagram — 64 Mb
CS#
CK/CK#
RWDS
DQ[7:0]
I/O
RESET#
Control
Logic
Block Diagram — 128 Mb
CS#
CK/CK#
RWDS
DQ[7:0]
CS#
CK/CK#
RWDS
DQ[7:0]
RESET#
I/O
Memory
Y Decoders
Data Latch
Data Path
HyperRAM 1
Control
Logic
Memory
Y Decoders
Data Latch
Data Path
RESET#
CS#
CK/CK#
RWDS
DQ[7:0]
RESET#
I/O
HyperRAM 2
Control
Logic
Memory
Y Decoders
Data Latch
Data Path
Document Number: 001-97964 Rev. *L
Page 2 of 51


Part Number S27KL0641
Description Self-Refresh DRAM
Maker Cypress Semiconductor
Total Page 30 Pages
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