Download S6E1C31B0A Datasheet PDF
Cypress
S6E1C31B0A
S6E1C31B0A is Microcontroller manufactured by Cypress.
- Part of the S6E1C3 comparator family.
Features 32-bit ARM Cortex-M0+ Core - Processor version: r0p1 - Maximum operating frequency: 40.8 MHz - Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 24 peripheral interrupt with 4 selectable interrupt priority levels - 24-bit System timer (Sys Tick): System timer for OS task management Bit Band Operation patible with Cortex-M3 bit band operation. On-Chip Memory - Flash memory  Up to 128 Kbytes  Read cycle: 0 wait-cycle  Security function for code protection - SRAM The on-chip SRAM of this series has one independent SRAM .  Up to 16 Kbytes  4Kbytes: can retain value in Deep standby Mode USB Interface USB interface is posed of Device and Host With Main PLL, USB clock can be generated by multiplication of Main clock. - USB Device  USB 2.0 Full-Speed supported  Max 6 End Point supported - End Point 0 is control transfer - End Point 1, 2 can be selected Bulk-transfer, Interrupt-transfer or Isochronous-transfer - End Point 3 to 5 can select Bulk-transfer or Interrupt-transfer - End Point 1 to 5 prise Double Buffer - The size of each End Point is according to the follows - End Point 0, 2 to 5 : 64 bytes - End Point 1 : 256 bytes - USB host  USB 2.0 Full/Low-Speed supported  Bulk-transfer, Interrupt-transfer and Isochronous-transfer support  USB Device connected/disconnected automatically detect  IN/OUT token handshake packet automatically  Max 256-byte packet-length supported  Wake-up function supported Multi-Function Serial Interface (Max 6channels) - 3 channels with 64Byte FIFO (Ch.4, 6 and 7), 3 channels without FIFO (Ch.0, 1 and 3) - The operation mode of each channel can be selected from one of the following.  UART  CSIO (CSIO is known to many customers as SPI)  I2C - UART  Full duplex double buffer  Parity can be enabled or disabled.  Built-in dedicated baud rate generator  External clock available as a serial clock  Hardware Flow control- : Automatically control the transmission by CTS/RTS (only ch.4) - : S6E1C32B0A/S6E1C31B0A...