S6J311E
Key Features
- This section explains the features of the S6J3110 series. Cortex-R5 Core This section explains the Cortex-R5 CPU core
- Arm® Cortex®-R5
- 32-bit Arm architecture 2-instruction issuance super scalar 8-stage pipeline
- Arm v7/Thumb®-2 instruction set
- MPU (memory protection) equipped 16-area support
- ECC support for the TCM ports for RAM 1-bit error correction and 2-bit error detection (SEC-DED)
- TCM ports 2 TCM ports
- BTCM port (B0TCM, B1TCM)
- Caches Instruction cache 16 KB Data cache 16 KB
- VIC port Low latency interrupt
