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Cypress Semiconductor Electronic Components Datasheet

W48C111-16 Datasheet

Frequency Generator

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PRELIMINARY
W48C111-16
Frequency Generator for Integrated Core Logic
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
• Power-on default to spread mode
• Two copies of CPU output
• Six copies of PCI output (synchronous w/CPU outputs)
• One copy of 48-MHz USB output
• One Buffered copy of 14.318-MHz input reference signal
• Supports 100-MHz or 66-MHz CPU operation
• Power management control input pins
• Low Frequency Test Mode
• Available in 28-pin SSOP (209 mil)
Key Specifications
Supply Voltages: ....................................... VDDQ3 = 3.3V±5%
VDDQ2 = 2.5V±5%
Block Diagram
VDDQ3
REF
X1 XTAL
X2 OSC
PLL Ref Freq
CPU_STOP#
SEL100/66#
PLL 1
Stop
Clock
Control
÷2/÷3
PCI_STOP#
Stop
Clock
Control
PWR_DWN#
Power
Down
Control
PLL 2
VDDQ2
CPU0
CPU1
VDDQ3
PCI_F
PCI1
PCI2
PCI3
VDDQ3
PCI4
PCI5
VDDQ3
48MHz
CPU0:1 Skew: ............................................................ 175 ps
CPU0:1 Cycle to Cycle Jitter: ..................................... 200 ps
PCI_F, PCI1:5 Skew: ...................................................500 ps
PCI_F, PCI1:5 Cycle to Cycle Jitter: ............................ 250 ps
CPU to PCI Skew: ........................ 1.5 to 4.0 ns (CPU Leads)
Output Duty Cycle: .................................................... 45/55%
PCI_F, PCI Edge Rate: .............................................. >1 V/ns
CPU_STOP#, PWR_DWN#, PCI_STOP#: 250-kpull-up
resistor
Table 1. Pin Selectable Frequency
SEL100/66#
CPU(0:1)
PCI
0
66.6 MHz
33.3
1
100 MHz
33.3
Spread%
±0.5%
±0.5%
Pin Configuration
X1
X2
GND
PCI_F
PCI1
VDDQ3
PCI2
PCI3
VDDQ3
PCI4
PCI5
GND
VDDQ3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
VDDQ3
REF
VDDQ2
CPU0
CPU1
GND
VDDQ3
GND
PCI_STOP#
CPU_STOP#
PWR_DWN#
48MHz
SEL100/66#
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
November 2, 1999, rev. **


Cypress Semiconductor Electronic Components Datasheet

W48C111-16 Datasheet

Frequency Generator

No Preview Available !

PRELIMINARY
W48C111-16
Pin Definitions
Pin Name
CPU0:1
Pin
No.
24, 23
PCI1:5
PCI_F
5, 7, 8, 10,
11
4
48MHz
CPU_STOP#
16
18
PCI_STOP#
19
REF
SEL100/66#
X1
X2
PWR_DWN#
26
15
1
2
17
VDDQ3
VDDQ2
GND
6, 9, 13, 21,
27
25
3, 12, 14, 20,
22, 28
Pin
Type
O
O
O
O
I
I
O
I
I
I
I
P
P
G
Pin Description
CPU Clock Outputs 0 and 1: These two CPU clock outputs are controlled by the
CPU_STOP# control pin. Output voltage swing is controlled by voltage applied to
VDDQ2.
PCI Bus Clock Outputs 1 through 5: These five PCI clock outputs are controlled
by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied
to VDDQ3.
Fixed PCI Clock Output: Unlike PCI1:5 outputs, this output is not controlled by the
PCI_STOP# control pin; it cannot be forced LOW by PCI_STOP#. Output voltage
swing is controlled by voltage applied to VDDQ3.
48-MHz Output: Fixed clock output at 48 MHz. Output voltage swing is controlled by
voltage applied to VDDQ3. This output does not have the SS feature
CPU_STOP# input: When brought LOW, clock outputs CPU0:1 are stopped LOW
after completing a full clock cycle (23 CPU clock latency). When brought HIGH,
clock outputs CPU0:1 start with a full clock cycle (23 CPU clock latency).
PCI_STOP# input: The PCI_STOP# input enables the PCI1:5 outputs when HIGH
and causes them to remain at logic 0 when LOW. The PCI_STOP signal is latched
on the rising edge of PCI_F. Its effect takes place on the next PCI_F clock cycle.
Fixed 14.318-MHz Output: Used for various system applications. Output voltage
swing is controlled by voltage applied to VDDQ3.
Frequency Selection Inputs: Select power-up default CPU clock frequency as
shown in Table 1 on page 1.
Crystal Connection or External Reference Frequency Input: This pin can either
be used as a connection to a crystal or to a reference signal.
Crystal Connection: An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
Power-Down Control: When this input is LOW, device goes into a low-power stand-
by condition. All outputs are held LOW. CPU and PCI clock outputs are stopped LOW
after completing a full clock cycle (23 CPU clock cycle latency). When brought
HIGH, CPU and PCI outputs start with a full clock cycle at full operating frequency
(3 ms maximum latency).
Power Connection: Connected to 3.3V supply.
Power Connection: Power supply for CPU0:1 output buffer. Connected to 2.5V or
3.3V.
Ground Connection: Connect all ground pins to the common system ground plane.
2


Part Number W48C111-16
Description Frequency Generator
Maker Cypress Semiconductor
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W48C111-16 Datasheet PDF






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