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Cypress Semiconductor Electronic Components Datasheet

W48S101-04 Datasheet

Spread Spectrum Motherboard Frequency Generator

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PRELIMINARY
W48S101-04
Spread Spectrum Motherboard Frequency Generator
Features
Key Specifications
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
I2C™ interface
Four copies of CPU output
Eight copies of PCI clock (synchronous w/CPU output)
Two copies of 14.318-MHz IOAPIC output
One copy of 48-MHz USB output
Selectable 24-/48-MHz clock-through-resistor
strapping
Three buffered copies of 14.318-MHz reference input
Input is a 14.318-MHz XTAL or reference signal
Selectable 100-MHz or 66-MHz CPU outputs
• Power management control input pins
• Test mode and output three-state through I2C interface
Supply Voltages:....................................... VDDQ3 = 3.3V±5%
VDDQ2 = 2.5V±5%
CPU Cycle to Cycle Jitter: ........................................... 200 ps
CPU0:3 Output Skew: ................................................ 175 ps
PCI_F, PCI1:7 Output Skew: .......................................500 ps
CPU to PCI Output Skew: ............ 1.5 to 4.0 ns (CPU Leads)
Logic inputs and REF0/SEL48# have 250K pull-up resistors
except SEL100/66#.
Table 1. Pin Selectable Frequency
SEL
100/66#
PCI
CPU (MHz) (MHz)
SPREAD#=0
0
66.8
33.4
±0.5% Center
1
100
33.3
±0.5% Center
Block Diagram
X1
X2
VDDCORE0/1
GNDCORE0/1
XTAL
OSC
PLL Ref Freq
CPU_STOP#
100/66#_SEL
SPREAD#
PCI_STOP#
Stop
Clock
Control
PLL 1
÷2/÷3
Stop
Clock
Control
SDATA
SCLK
PWR_DWN#
I2C
Logic
Power
Down
Control
PLL2
I2C is a trademark of Philips Corporation.
VDDREF
REF0/SEL48#
REF1
REF2
GNDREF
VDDAPIC
APIC0
APIC1
GNDAPIC
VDDCPU0
CPU0
CPU1
GNDCPU0
VDDCPU1
CPU2
CPU3
GNDCPU1
VDDPCI0
PCI_F
PCI1
PCI2
PCI3
GNDPCI0
VDDPCI1
PCI4
PCI5
PCI6
PCI7
GNDPCI1
VDD48MHz
48MHz
24/48MHz
GND48MHz
Pin Configuration[1]
REF0/SEL48#
REF1
GNDREF
X1
X2
GNDPCI0
PCICLK_F
PCI1
VDDPCI0
PCI2
PCI3
GNDPCI1
PCI4
PCI5
VDDPCI1
PCI6
PCI7
GNDPCI2
VDDCORE0
GNDCORE0
VDD48MHz
48MHz
24/48MHz
GND48MHz
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDREF
47 REF2
46 VDDAPIC
45 APIC0
44 APIC1
43 GNDAPIC
42 NC
41 VDDCPU0
40 CPU0
39 CPU1
38 GNDCPU0
37 VDDCPU1
36 CPUCLK2
35 CPUCLK3
34 GNDCPU1
33 VDDCORE1
32 GNDCORE1
31 PCI_STOP#
30 CPU_STOP#
29 PWR_DWN#
28 SPREAD#
27 SDATA
26 SCLK
25 SEL100/66#
Note:
1. Internal pull-up resistors should not be relied upon for
setting I/O pins HIGH.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 27, 1999, rev. **


Cypress Semiconductor Electronic Components Datasheet

W48S101-04 Datasheet

Spread Spectrum Motherboard Frequency Generator

No Preview Available !

PRELIMINARY
W48S101-04
Pin Definitions
Pin Name
Pin No.
CPU0:3
40, 39, 36,
35
PCI1:7
PCI_F
8, 10, 11,
13, 14, 16,
17
7
CPU_STOP#
30
PCI_STOP#
31
SPREAD#
APIC0:1
48MHz
24/48MHz
28
45, 44
22
23
REF0/SEL48#
1
REF1:2
SEL100/66#
SCLK
SDATA
X1
2, 47
25
26
27
4
X2
PWR_DWN#
5
29
VDDQ3
VDDQ2
GND
9, 15, 19,
21, 33, 48
46, 41, 37
3, 6, 12, 18,
20, 24, 32,
34, 38, 43
Pin Type
O
O
O
I
I
I
O
O
O
I/O
O
I
I
I/O
I
I
I
P
Pin Description
CPU Clock Outputs 0 through 3: These four CPU clock outputs are controlled by
the CPU_STOP# control pin. Output voltage swing is controlled by voltage applied
to VDDQ2.
PCI Bus Clock Outputs 1 through 7: These seven PCI clock outputs are controlled
by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied
to VDDQ3.
Fixed PCI Clock Output: Unlike PCI1:7 outputs, this output is not controlled by the
PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to
VDDQ3.
CPU_STOP# Input: When brought LOW, clock outputs CPU0:3 are stopped LOW
after completing a full clock cycle (23 CPU clock latency). When brought HIGH,
clock outputs CPU0:3 start beginning with a full clock cycle (23 CPU clock latency).
PCI_STOP# Input: The PCI_STOP# input enables the PCI 1:7 outputs when HIGH
and causes them to remain at logic 0 when LOW. The PCI_STOP signal is latched
on the rising edge of PCI_F. Its effect takes place on the next PCI_F clock cycle.
SPREAD# Input: When brought LOW this pin activates Spread Spectrum clocking.
I/O APIC Clock Outputs: Provides 14.318-MHz fixed frequency. The output voltage
swing is controlled by VDDQ2.
48-MHz Output: Fixed clock outputs at 48 MHz. Output voltage swing is controlled
by voltage applied to VDDQ3.
24-MHz or 48-MHz Output: 24-MHz output when pin 1 is strapped through 10-k
resistor to VDDQ3. 48-MHz output when pin 1 is strapped through 10-kresistor to
GND.
I/O Dual Function REF0 and SEL48# pin: During power on, SEL48# input will be
latched, which will set pin 23 to output 24 MHz or 48 MHz. It then reverts to REF0
fixed output.
Fixed 14.318-MHz Outputs 1 through 2: Used for various system applications.
Output voltage swing is controlled by voltage applied to VDDQ3.
Frequency Selection Input: Selects power-up default CPU clock frequency as
shown in Table 1 on page 1.
Clock pin for I2C circuitry.
Data pin for I2C circuitry.
Crystal Connection or External Reference Frequency Input: This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an
external reference frequency input.
Crystal Connection: An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
Power Down Control: When this input is LOW, device goes into a low-power stand-
by condition. All outputs are actively held LOW while in power-down. CPU and PCI
clock outputs are stopped LOW after completing a full clock cycle (23 CPU clock
cycle latency). When brought HIGH, CPU, SDRAM and PCI outputs start with a full
clock cycle at full operating frequency (3 ms maximum latency).
Power Connection: Connect to 3.3V supply.
P Power Connection: Power supply for APIC0:1 and CPU0:3 output buffers. Connect
to 2.5V.
G Ground Connections: Connect all ground pins to the common system ground
plane.
2


Part Number W48S101-04
Description Spread Spectrum Motherboard Frequency Generator
Maker Cypress Semiconductor
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W48S101-04 Datasheet PDF






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Cypress Semiconductor





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